From patchwork Wed Feb 24 15:14:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 587495 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1F773140B95 for ; Thu, 25 Feb 2016 02:14:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751845AbcBXPOj (ORCPT ); Wed, 24 Feb 2016 10:14:39 -0500 Received: from down.free-electrons.com ([37.187.137.238]:40888 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752109AbcBXPOh (ORCPT ); Wed, 24 Feb 2016 10:14:37 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 440261114; Wed, 24 Feb 2016 16:14:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (AToulouse-657-1-984-111.w86-217.abo.wanadoo.fr [86.217.138.111]) by mail.free-electrons.com (Postfix) with ESMTPSA id 10B2811D; Wed, 24 Feb 2016 16:14:36 +0100 (CET) From: Thomas Petazzoni To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala Cc: Nadav Haklai , Lior Amsalem , Neta Zur Hershkovits , Yehuda Yitschak , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni Subject: [PATCH v2 2/6] dt-bindings: clock: add DT bindings for AP806 core clocks Date: Wed, 24 Feb 2016 16:14:22 +0100 Message-Id: <1456326866-30854-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1456326866-30854-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1456326866-30854-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the Device Tree binding description for the AP806 core clocks, used on Marvell Armada 7K/8K SOCs. Since the AP806 core clocks register is part of the "DFX Server" register area, the DT binding is meant to be used as a sub-node of the DFX Server DT binding, which is described separately. Signed-off-by: Thomas Petazzoni --- .../clock/mvebu-armada-ap806-core-clock.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-armada-ap806-core-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-core-clock.txt new file mode 100644 index 0000000..996c47f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-core-clock.txt @@ -0,0 +1,35 @@ +* Clock bindings for Marvell MVEBU AP806 Core clocks + +The Marvell MVEBU Armada 7K/8K SoCs contain a block called AP806, +hosting the CPU and other core components of the CPU. This Device Tree +binding allows to describe the core clocks of the AP806, whose +frequencies are determined by reading the Sample-At-Reset (SAR) +register. This register is part of the DFX server register area, +covered by the DT binding described at +Documentation/devicetree/bindings/arm/marvell/marvell,ap806-dfx-server.txt. Therefore, +the DT node for the AP806 Core clocks must appear as a child node of +the DFX server Device Tree node. + +Clock consumers must specify the desired clock by having the clock ID +in its "clocks" phandle cell. + +The following is a list of provided IDs and clock names for the core +Armada AP806 clocks: + + 0 = DDR + 1 = Ring + 2 = CPU + +Required properties: +- compatible: must be be one of the following: + "marvell,armada-ap806-core-clock" +- #clock-cells: from common clock binding; shall be set to 1 +- clock-output-names: name of the output clocks + +Example: + + coreclk: clk@204 { + compatible = "marvell,armada-ap806-core-clock"; + #clock-cells = <1>; + clock-output-names = "ddr", "ring", "cpu"; + };