From patchwork Mon Feb 15 07:34:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 582771 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 56AB714030E for ; Mon, 15 Feb 2016 18:35:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752491AbcBOHf1 (ORCPT ); Mon, 15 Feb 2016 02:35:27 -0500 Received: from down.free-electrons.com ([37.187.137.238]:49086 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751721AbcBOHfX (ORCPT ); Mon, 15 Feb 2016 02:35:23 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 4217DE86; Mon, 15 Feb 2016 08:35:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (AToulouse-657-1-45-133.w92-156.abo.wanadoo.fr [92.156.219.133]) by mail.free-electrons.com (Postfix) with ESMTPSA id 042E2226; Mon, 15 Feb 2016 08:35:21 +0100 (CET) From: Thomas Petazzoni To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Nadav Haklai , Lior Amsalem , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni Subject: [PATCH 3/3] clk: mvebu: add AP806 ring clock driver Date: Mon, 15 Feb 2016 08:34:58 +0100 Message-Id: <1455521698-7905-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1455521698-7905-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1455521698-7905-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds a new driver to handle the ring clocks found in the AP806 HW block, which is the core block of all Armada 7K and 8K Marvell 64-bits processors. Those ring clocks are derived from the core ring clock handled by the AP806 core clock driver. The ring clocks are used by various peripherals inside the AP806. Signed-off-by: Thomas Petazzoni --- .../clock/mvebu-armada-ap806-ring-clock.txt | 32 +++++++++++ drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/ap806-ring.c | 65 ++++++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-armada-ap806-ring-clock.txt create mode 100644 drivers/clk/mvebu/ap806-ring.c diff --git a/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-ring-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-ring-clock.txt new file mode 100644 index 0000000..5602bdc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-armada-ap806-ring-clock.txt @@ -0,0 +1,32 @@ +* Clock bindings for Marvell MVEBU AP806 Ring clocks + +The Marvell MVEBU Armada 7K/8K SoCs contain a block called AP806, +hosting the CPU and other core components of the CPU. This Device Tree +binding allows to describe the ring clocks of the AP806, which are +derived from the Ring Core clock, after a dividing factor. + +The following is a list of provided IDs and clock names on Armada +AP806 RING dividers: + + 0 = Ring 0 + 1 = Ring 2 + 2 = Ring 3 + 3 = Ring 4 + 4 = Ring 5 + +Required properties: +- compatible: must be one of the following: + "marvell,armada-ap806-ring-clock" +- reg: must be the register holding the divider values for ring clocks +- #clock-cells : from common clock binding; shall be set to 1 +- clock-output-names: name of the output clocks + +Example: + + ringclk: clk@0x6F8250 { + compatible = "marvell,armada-ap806-ring-clock"; + reg = <0x6F8250 0x04>; + #clock-cells = <1>; + clock-output-names = "ring-0", "ring-2", "ring-3", "ring-4", "ring-5"; + clocks = <&coreclk 1>; + }; diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig index fd84172..5d30aac 100644 --- a/drivers/clk/mvebu/Kconfig +++ b/drivers/clk/mvebu/Kconfig @@ -45,3 +45,6 @@ config ORION_CLK config ARMADA_AP806_CORE_CLK bool + +config ARMADA_AP806_RING_CLK + bool diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index db5c28c..48ca2d3 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_AP806_CORE_CLK) += ap806-core.o +obj-$(CONFIG_ARMADA_AP806_RING_CLK) += ap806-ring.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o diff --git a/drivers/clk/mvebu/ap806-ring.c b/drivers/clk/mvebu/ap806-ring.c new file mode 100644 index 0000000..154ee55 --- /dev/null +++ b/drivers/clk/mvebu/ap806-ring.c @@ -0,0 +1,65 @@ +/* + * Marvell Armada AP806 ring clocks + * + * Copyright (C) 2016 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#define AP806_RING_DIV_NUM 5 + +static struct clk *ap806_ring_clks[AP806_RING_DIV_NUM]; + +static struct clk_onecell_data ap806_ring_clk_data = { + .clks = ap806_ring_clks, + .clk_num = AP806_RING_DIV_NUM, +}; + +static void __init ap806_ring_clk_init(struct device_node *np) +{ + void __iomem *base; + const char *parent; + u32 reg; + int i; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + reg = readl(base); + + iounmap(base); + + parent = of_clk_get_parent_name(np, 0); + + for (i = 0; i < AP806_RING_DIV_NUM; i++) { + unsigned long divider; + const char *name; + + /* Each clock is represented by 6 bits */ + divider = (reg >> (6 * i)) & 0x3f; + + of_property_read_string_index(np, "clock-output-names", + i, &name); + + ap806_ring_clks[i] = + clk_register_fixed_factor(NULL, name, parent, + 0, 1, divider); + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_ring_clk_data); +} + +CLK_OF_DECLARE(ap806_ring_clk, "marvell,armada-ap806-ring-clock", + ap806_ring_clk_init);