From patchwork Sat Oct 17 17:27:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 531825 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2B7A01402B7 for ; Sun, 18 Oct 2015 04:28:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964781AbbJQR2E (ORCPT ); Sat, 17 Oct 2015 13:28:04 -0400 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:59557 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753453AbbJQR1W (ORCPT ); Sat, 17 Oct 2015 13:27:22 -0400 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id EE36620772; Sun, 18 Oct 2015 01:27:13 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id C5D2C5F924; Sun, 18 Oct 2015 01:27:13 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Mark Brown , Arnd Bergmann Subject: [PATCH v6 1/2] bus: sunxi-rsb: Add Allwinner Reduced Serial Bus (RSB) controller bindings Date: Sun, 18 Oct 2015 01:27:09 +0800 Message-Id: <1445102830-21774-2-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445102830-21774-1-git-send-email-wens@csie.org> References: <1445102830-21774-1-git-send-email-wens@csie.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reduced Serial Bus is a proprietary 2-line push-pull serial bus supporting multiple slave devices. It was developed by Allwinner, Inc. and used by Allwinner and X-Powers, Inc. for their line of PMICs and other peripheral ICs. Recent Allwinner SoCs, starting with the A23, have an RSB controller. This is used to talk to the PMIC, and later with the A80 and A83 platform, the audio codec IC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../devicetree/bindings/bus/sunxi-rsb.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/sunxi-rsb.txt diff --git a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt new file mode 100644 index 000000000000..3dd28343b6ce --- /dev/null +++ b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt @@ -0,0 +1,47 @@ +Allwinner Reduced Serial Bus (RSB) controller + +The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire +serial bus with 1 master and up to 15 slaves. It is represented by a node +for the controller itself, and child nodes representing the slave devices. + +Required properties : + + - reg : Offset and length of the register set for the controller. + - compatible : Shall be "allwinner,sun8i-a23-rsb". + - interrupts : The interrupt line associated to the RSB controller. + - clocks : The gate clk associated to the RSB controller. + - resets : The reset line associated to the RSB controller. + - #address-cells : shall be 1 + - #size-cells : shall be 0 + +Optional properties : + + - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz. + If not set this defaults to 3MHz. + +Child nodes: + +An RSB controller node can contain zero or more child nodes representing +slave devices on the bus. Child 'reg' properties should contain the slave +device's hardware address. The hardware address is hardwired in the device, +which can normally be found in the datasheet. + +Example: + + rsb@01f03400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = <0 39 4>; + clocks = <&apb0_gates 3>; + clock-frequency = <3000000>; + resets = <&apb0_rst 3>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@3e3 { + compatible = "..."; + reg = <0x3e3>; + + /* ... */ + }; + };