From patchwork Mon Jul 6 19:10:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 491782 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 84D6C140285 for ; Tue, 7 Jul 2015 05:12:15 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=DzvUZpC3; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755272AbbGFTL5 (ORCPT ); Mon, 6 Jul 2015 15:11:57 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:37814 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752671AbbGFTLC (ORCPT ); Mon, 6 Jul 2015 15:11:02 -0400 Received: by wiclp1 with SMTP id lp1so30279572wic.0; Mon, 06 Jul 2015 12:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nGvnaq86BkwT3ohj2XuhaGD5DRkh3P+JCuDKCUPeRfM=; b=DzvUZpC3A23P6ks6dPiXy4HrUDrMfgmPl+ZT4DQ3LlUrT7VAqRRKxQCavKT2205kCH N2qkNW9sgiZ3UamzIpSGk+Tv6TkHtwt5oHNdOAEQ0w/nPQt4exb9NeQDix6UtiQdwa1/ zldhlf835Xq9crq2yj3os+LSMmT0tgoPDQarWTmKpyLwr9mh6yZG97Ncao56dBgDC9Vi 4BrxNIQaVEQZM4dVnUUZV4HF2GEKzyH9MFdaBfvTtAXSPFAIEGzjMUB+f83TaxIV3X4+ xLENs+/wAgyIDgEq0vLRz+3UX1qaVgT1DYam4+frmQ9gdCudmMJSa2wWB23RImr4TqEZ 7cbw== X-Received: by 10.180.198.199 with SMTP id je7mr56403713wic.34.1436209860442; Mon, 06 Jul 2015 12:11:00 -0700 (PDT) Received: from Red.local (ANice-651-1-256-42.w86-205.abo.wanadoo.fr. [86.205.160.42]) by mx.google.com with ESMTPSA id dl10sm26347629wjb.42.2015.07.06.12.10.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jul 2015 12:10:59 -0700 (PDT) From: LABBE Corentin To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, maxime.ripard@free-electrons.com, linux@arm.linux.org.uk, herbert@gondor.apana.org.au, davem@davemloft.net, akpm@linux-foundation.org, gregkh@linuxfoundation.org, mchehab@osg.samsung.com, arnd@arndb.de, joe@perches.com Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, linux-sunxi@googlegroups.com, LABBE Corentin Subject: [PATCH v10 3/5] ARM: sun4i: dt: Add DT bindings documentation for SUN4I Security System Date: Mon, 6 Jul 2015 21:10:46 +0200 Message-Id: <1436209848-16530-4-git-send-email-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1436209848-16530-1-git-send-email-clabbe.montjoie@gmail.com> References: <1436209848-16530-1-git-send-email-clabbe.montjoie@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds documentation for Device-Tree bindings for the Security System cryptographic accelerator driver. Signed-off-by: LABBE Corentin --- Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/sun4i-ss.txt diff --git a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt new file mode 100644 index 0000000..1e02d17 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt @@ -0,0 +1,19 @@ +* Allwinner Security System found on A20 SoC + +Required properties: +- compatible : Should be "allwinner,sun4i-a10-crypto". +- reg: Should contain the Security System register location and length. +- interrupts: Should contain the IRQ line for the Security System. +- clocks : List of clock specifiers, corresponding to ahb and ss. +- clock-names : Name of the functional clock, should be + * "ahb" : AHB gating clock + * "mod" : SS controller clock + +Example: + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ahb_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + };