From patchwork Thu May 7 14:00:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bintian Wang X-Patchwork-Id: 469699 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 544CF140283 for ; Thu, 7 May 2015 23:57:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751174AbbEGN54 (ORCPT ); Thu, 7 May 2015 09:57:56 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:40887 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750863AbbEGN5z (ORCPT ); Thu, 7 May 2015 09:57:55 -0400 Received: from 172.24.2.119 (EHLO szxeml433-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BFR60501; Thu, 07 May 2015 21:56:06 +0800 (CST) Received: from localhost.localdomain (10.110.52.31) by szxeml433-hub.china.huawei.com (10.82.67.210) with Microsoft SMTP Server id 14.3.158.1; Thu, 7 May 2015 21:55:57 +0800 From: Bintian Wang To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v5 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART Date: Thu, 7 May 2015 22:00:23 +0800 Message-ID: <1431007225-8513-5-git-send-email-bintian.wang@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1431007225-8513-1-git-send-email-bintian.wang@huawei.com> References: <1431007225-8513-1-git-send-email-bintian.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.110.52.31] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.554B6EF7.011B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2db945286f198500e5a12f3ca87dfebb Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string "hisilicon,hi6220-uart" for future optimisations or workarounds works. Signed-off-by: Bintian Wang Suggested-by: Mark Rutland --- Documentation/devicetree/bindings/serial/pl011.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8..cb9fd9d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,9 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: should contain one of the following sequences: + * "arm,pl011", "arm,primecell" + * "hisilicon,hi6220-pl011", "arm,pl011", "arm,primecell" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier