From patchwork Wed May 6 17:59:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 469091 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 69E5E1402B5 for ; Thu, 7 May 2015 04:02:19 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=fP/DJs0K; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752817AbbEFSBK (ORCPT ); Wed, 6 May 2015 14:01:10 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:33645 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752786AbbEFSBG (ORCPT ); Wed, 6 May 2015 14:01:06 -0400 Received: by pdbnk13 with SMTP id nk13so16614995pdb.0; Wed, 06 May 2015 11:01:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P8yApZlHkCmkePzu76eIgzdh8ZC2O2hHK14nN4j8b4Q=; b=fP/DJs0KfOtPWjhSW99YOFN/DYqmzoBT+gSdR4/BeaU7rw0yI1rSuHku/w3U0SwhMR 8+nogC8ErUmxV6qYus4pPoRasTRnKhE0vd4EWcd2dOTH3SFu5zZg5PeMGXluvO8Cg9O9 CuxHYLtQkhgvaKTstivssDcUa9QlAaZ/dHNERunhwyCYlMZQczAnX4Ry+yU4JULA0iEe ijO9fvz1kIwhoOshDdTRtGy48wXjeG8OMHOFPmv1ZLmQOY8gHeKcGl/tr8zRUq8UxOsC 9T6Q7a+v01r2HciPJHsRKwtCYV5w/0QTspAJGA7mVWUYtVFpHb/HQtDxBn/jFHSruHCk jMKQ== X-Received: by 10.68.246.133 with SMTP id xw5mr38015927pbc.116.1430935265880; Wed, 06 May 2015 11:01:05 -0700 (PDT) Received: from ld-irv-0074.broadcom.com (5520-maca-inet1-outside.broadcom.com. [216.31.211.11]) by mx.google.com with ESMTPSA id xz3sm2484294pbc.13.2015.05.06.11.01.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 May 2015 11:01:05 -0700 (PDT) From: Brian Norris To: Cc: Brian Norris , Dmitry Torokhov , Anatol Pomazao , Ray Jui , Corneliu Doban , Jonathan Richardson , Scott Branden , Florian Fainelli , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , bcm-kernel-feedback-list@broadcom.com, Dan Ehrenberg , Gregory Fong , , , Kevin Cernekee Subject: [PATCH v3 05/10] Documentation: devicetree: brcmstb_nand: add 'brcm, nand-soc' bindings Date: Wed, 6 May 2015 10:59:49 -0700 Message-Id: <1430935194-7579-6-git-send-email-computersforpeace@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430935194-7579-1-git-send-email-computersforpeace@gmail.com> References: <1430935194-7579-1-git-send-email-computersforpeace@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Brian Norris --- .../devicetree/bindings/mtd/brcm,brcmstb-nand.txt | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt index 662c857e74fe..6a3ab751db99 100644 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt @@ -30,7 +30,10 @@ Required properties: "flash-dma" and/or "nand-cache". - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) FLASH_DMA_DONE -- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" +- interrupt-names : For hardware without a dedicated 'brcm,nand-soc' node, may + be "nand_ctlrdy" or "flash_dma_done" + For hardware with a dedicated 'brcm,nand-soc' node for + breaking out individual interrupt types, may be "nand" - interrupt-parent : See standard interrupt bindings - #address-cells : <1> - subnodes give the chip-select number - #size-cells : <0> @@ -40,6 +43,10 @@ Optional properties: (WP) control bit. It is always available on >= v7.0. Use this property to describe the rare earlier versions of this core that include WP +- brcm,nand-soc : Phandle to SoC control node. This is necessary + for SoCs where NAND interrupts and bus + infrastructure are integrated in non-standard + ways. * NAND chip-select @@ -74,6 +81,36 @@ Optional properties: Each nandcs device node may optionally contain sub-nodes describing the flash partition mapping. See partition.txt for more detail. + +* NAND SoC control node: + +The NAND controller is integrated differently on the variety of SoCs on which it +is found. Part of this integration involves providing status and enable bits +with which to control the 8 exposed NAND interrupts, as well as hardware for +configuring the endianness of the data bus. On some SoCs, these features are +handled via standard, modular components (e.g., their interrupts look like a +normal IRQ chip), but on others, they are controlled in unique and interesting +ways, sometimes with registers that lump multiple NAND-related functions +together. The former case can be described simply by the standard interrupts +properties in the main controller node. But for the latter exceptional cases, +we can describe these extra SoC-specific integration hardware via the following +node, referenced from the brcm,brcmnand node above. + + - compatible: Can be one of several SoC-specific strings. Each SoC may have + different requirements for its additional properties, as described below each + bullet point below. + + * "brcm,nand-soc-bcm63138" + - reg: (required) the 'NAND_INT_BASE' register range, with separate status + and enable registers + + * "brcm,nand-soc-iproc" + - reg: (required) the "IDM" register range, for interrupt enable and APB + bus access endianness configuration, and the "EXT" register range, + for interrupt status/ack. + - reg-names: (required) a list of the names corresponding to the previous + register ranges. Should contain "idm" and "ext". + Example: nand@f0442800 {