From patchwork Wed May 6 08:37:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Fong X-Patchwork-Id: 468617 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F092D1402AB for ; Wed, 6 May 2015 18:39:06 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=mHkDWMlM; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752430AbbEFIjE (ORCPT ); Wed, 6 May 2015 04:39:04 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:34037 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751997AbbEFIjA (ORCPT ); Wed, 6 May 2015 04:39:00 -0400 Received: by pacyx8 with SMTP id yx8so3251741pac.1; Wed, 06 May 2015 01:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aRwr2hoVGRVQEVNVWFcVibXZNxtUnQt7U0IsFdQIQtE=; b=mHkDWMlMRROOA7aWdoZMRyIaVS8/C7A9HKD04rbYHHMGNy8pKxwjKh8cVLRFme8qUS EmpqlPEAvzYtJRtXs8CBliLx/T+LopRT2v8KXEl9br7jkVqU2Gfelio8/KthArx4EGp4 SFCErJqNHqL91PBkCiaNl48gJ5nxT40llvCjmTer3fkbCD+1BV34CS8XJUux1GUZEVHI JK/t9d3zL9OqhkjhHkHsoXs4X/IqBc0R1/HDtVoEopji8d911hjoupzhPV92BIh8seKc 9Ji9HNhzGYxiki389ZQo9eCYjXQLsKZJPnZYaqHYj9crLDHwG2tGpFG4wjkADA/iTGKb 3S8Q== X-Received: by 10.70.98.171 with SMTP id ej11mr58894129pdb.72.1430901540402; Wed, 06 May 2015 01:39:00 -0700 (PDT) Received: from corellia.google.com (cpe-98-148-132-5.socal.res.rr.com. [98.148.132.5]) by mx.google.com with ESMTPSA id ry2sm1162416pbb.83.2015.05.06.01.38.58 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 May 2015 01:38:59 -0700 (PDT) From: Gregory Fong To: linux-gpio@vger.kernel.org Cc: Gregory Fong , Alexandre Courbot , bcm-kernel-feedback-list@broadcom.com, Brian Norris , devicetree@vger.kernel.org, Florian Fainelli , Ian Campbell , Kumar Gala , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland , Pawel Moll , Rob Herring , Russell King Subject: [PATCH 1/3] dt-bindings: add brcmstb-gpio GPIO binding Date: Wed, 6 May 2015 01:37:55 -0700 Message-Id: <1430901477-10678-2-git-send-email-gregory.0xf0@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1430901477-10678-1-git-send-email-gregory.0xf0@gmail.com> References: <1430901477-10678-1-git-send-email-gregory.0xf0@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for Broadcom STB "UPG GIO" GPIO controller. Signed-off-by: Gregory Fong --- .../devicetree/bindings/gpio/brcm,brcmstb-gpio.txt | 65 ++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt new file mode 100644 index 0000000..435f1bc --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt @@ -0,0 +1,65 @@ +Broadcom STB "UPG GIO" GPIO controller + +The controller's registers are organized as sets of eight 32-bit +registers with each set controlling a bank of up to 32 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: + +- compatible: + Must be "brcm,brcmstb-gpio" + +- reg: + Define the base and range of the I/O address space containing + the brcmstb GPIO controller registers + +- #gpio-cells: + Should be <2>. The first cell is the pin number (within the controller's + pin space), and the second is used for the following: + bit[0]: polarity (0 for active-high, 1 for active-low) + +- gpio-controller: + Specifies that the node is a GPIO controller. + +- brcm,gpio-bank-widths: + Number of GPIO lines for each bank. Number of elements must + correspond to number of banks suggested by the 'reg' property. + +Optional properties: + +- interrupts: + The interrupt shared by all GPIO lines for this controller. + +- interrupt-parent: + phandle of the parent interrupt controller + +- #interrupt-cells: + Should be <2>. The first cell is the GPIO number, the second should specify + flags. The following subset of flags is supported: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +- interrupt-controller: + Marks the device node as an interrupt controller + +- interrupt-names: + The name of the IRQ resource used by this controller + +Example: + upg_gio: gpio@f040a700 { + #gpio-cells = <0x2>; + #interrupt-cells = <0x2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf040a700 0x80>; + interrupt-parent = <0xf>; + interrupts = <0x6>; + interrupt-names = "upg_gio"; + brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>; + };