From patchwork Mon May 4 12:42:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 467603 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0A70E140295 for ; Mon, 4 May 2015 22:44:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753337AbbEDMnY (ORCPT ); Mon, 4 May 2015 08:43:24 -0400 Received: from ns.mm-sol.com ([37.157.136.199]:45569 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753283AbbEDMmZ (ORCPT ); Mon, 4 May 2015 08:42:25 -0400 Received: from localhost.localdomain (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 2DC9EC8D0; Mon, 4 May 2015 15:42:22 +0300 (EEST) From: Stanimir Varbanov To: Rob Herring , Kumar Gala , Mark Rutland , Grant Likely , Bjorn Helgaas , Kishon Vijay Abraham I , Russell King , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Mathieu Olivari , Srinivas Kandagatla , Stanimir Varbanov Subject: [PATCH v2 3/5] DT: PCI: qcom: Document PCIe devicetree bindings Date: Mon, 4 May 2015 15:42:16 +0300 Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1430743338-10441-1-git-send-email-svarbanov@mm-sol.com> References: <1430743338-10441-1-git-send-email-svarbanov@mm-sol.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov --- .../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++ 1 files changed, 231 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt new file mode 100644 index 0000000..dcf7348 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -0,0 +1,231 @@ +* Qualcomm PCI express root complex + +- compatible: + Usage: required + Value type: + Definition: Value shall include + - "qcom,pcie-v0" for apq/ipq8064 + - "qcom,pcie-v1" for apq8084 + +- reg: + Usage: required + Value type: + Definition: Register ranges as listed in the reg-names property + +- reg-names: + Usage: required + Value type: + Definition: Must include the following entries + - "parf" Qualcomm specific registers + - "dbi" Designware PCIe registers + - "elbi" External local bus interface registers + - "config" PCIe configuration space + +- device_type: + Usage: required + Value type: + Definition: Should be "pci". As specified in designware-pcie.txt + +- #address-cells: + Usage: required + Value type: + Definition: Should be set to 3. As specified in designware-pcie.txt + +- #size-cells: + Usage: required + Value type: + Definition: Should be set 2. As specified in designware-pcie.txt + +- ranges: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- interrupts: + Usage: required + Value type: + Definition: MSI interrupt + +- interrupt-names: + Usage: required + Value type: + Definition: Should contain "msi" + +- #interrupt-cells: + Usage: required + Value type: + Definition: Should be 1. As specified in designware-pcie.txt + +- interrupt-map-mask: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- interrupt-map: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- clocks: + Usage: required + Value type: + Definition: List of phandle and clock specifier pairs as listed + in clock-names property + +- clock-names: + Usage: required + Value type: + Definition: Should contain the following entries + * should be populated for v0 and v1 + - "iface" Configuration AHB clock + + * should be populated for v0 + - "core" Clocks the pcie hw block + - "phy" Clocks the pcie PHY block + + * should be populated for v1 + - "aux" Auxiliary (AUX) clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + +- resets: + Usage: required + Value type: + Definition: List of phandle and reset specifier pairs as listed + in reset-names property + +- reset-names: + Usage: required + Value type: + Definition: Should contain the following entries + * should be populated for v0 + - "axi" AXI reset + - "ahb" AHB reset + - "por" POR reset + - "pci" PCI reset + - "phy" PHY reset + + * should be populated for v1 + - "core" Core reset + +- power-domains: + Usage: required (for v1 only) + Value type: + Definition: A phandle and power domain specifier pair to the + power domain which is responsible for collapsing + and restoring power to the peripheral + +- -supply: + Usage: required + Value type: + Definition: List of phandles to the power supply regulator(s) + * should be populated for v0 and v1 + - "vdda" core analog power supply + + * should be populated for v0 + - "vdda_phy" analog power supply for PHY + - "vdda_refclk" analog power supply for IC which generate + reference clock + +- phys: + Usage: required (for v1 only) + Value type: + Definition: List of phandle(s) as listed in phy-names property + +- phy-names: + Usage: required (for v1 only) + Value type: + Definition: Should contain "pciephy" + +- -gpio: + Usage: optional + Value type: + Definition: List of phandle and gpio specifier pairs. Should contain + - "perst" PCIe endpoint reset signal line + - "pewake" PCIe endpoint wake signal line + +- pinctrl-0: + Usage: required + Value type: + Definition: List of phandles pointing at a pin(s) configuration + +- pinctrl-names + Usage: required + Value type: + Definition: List of names of pinctrl-0 state + +* Example for v0 + pcie0: pci@1b500000 { + compatible = "qcom,pcie-v0"; + reg = <0x1b500000 0x1000 + 0x1b502000 0x80 + 0x1b600000 0x100 + 0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ + 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */ + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_CLK>; + clock-names = "core", "iface", "phy"; + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy"; + }; + +* Example for v1 + pcie0@fc520000 { + compatible = "qcom,pcie-v1"; + reg = <0xfc520000 0x2000>, + <0xff000000 0x1000>, + <0xff001000 0x1000>, + <0xff002000 0x2000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ + 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>; + clock-names = "iface", "master_bus", "slave_bus", "aux"; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE0_GDSC>; + vdda-supply = <&pma8084_l3>; + phys = <&pciephy0>; + phy-names = "pciephy"; + perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins_default>; + pinctrl-names = "default"; + };