From patchwork Wed Mar 18 16:37:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 451537 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B72F61400B6 for ; Thu, 19 Mar 2015 03:38:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755960AbbCRQiM (ORCPT ); Wed, 18 Mar 2015 12:38:12 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:42369 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755607AbbCRQh3 (ORCPT ); Wed, 18 Mar 2015 12:37:29 -0400 Received: from ayla.of.borg ([84.193.93.87]) by andre.telenet-ops.be with bizsmtp id 54dT1q00u1t5w8s014dTrq; Wed, 18 Mar 2015 17:37:28 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1YYGyF-0007Vi-GC; Wed, 18 Mar 2015 17:37:27 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1YYGyH-0006g5-3T; Wed, 18 Mar 2015 17:37:29 +0100 From: Geert Uytterhoeven To: Thomas Gleixner , Jason Cooper Cc: linux-sh@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH] irqchip: renesas-intc-irqpin: Add optional functional clock to bindings Date: Wed, 18 Mar 2015 17:37:24 +0100 Message-Id: <1426696644-25636-1-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This clock is managed since commit 705bc96c2c15313c ("irqchip: renesas-intc-irqpin: Add minimal runtime PM support"). Also add an example while we're at. Signed-off-by: Geert Uytterhoeven --- .../interrupt-controller/renesas,intc-irqpin.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt index 4f7946ae8adcdc04..e7cfcec056159b93 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -25,3 +25,32 @@ Optional properties: if different from the default 4 bits - control-parent: disable and enable interrupts on the parent interrupt controller, needed for some broken implementations +- clocks: Must contain a reference to the functional clock. The property is + mandatory if the hardware implements a controllable functional clock for + the irqpin controller instance. + + +Example +------- + + irqpin1: irqpin@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", + "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + };