From patchwork Thu Feb 26 16:14:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 443980 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C6B441400D5 for ; Fri, 27 Feb 2015 03:14:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932272AbbBZQOa (ORCPT ); Thu, 26 Feb 2015 11:14:30 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:45379 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932263AbbBZQO2 (ORCPT ); Thu, 26 Feb 2015 11:14:28 -0500 Received: by pablf10 with SMTP id lf10so14967239pab.12 for ; Thu, 26 Feb 2015 08:14:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BWDr/plGEBQBPy8oUuEH08k9EN13DYGEliQA8C19xIk=; b=P5ioduhlUyWKGOJrygwxngtv2TYObFjCapImBiKCKU+l0y28ZlUszPioqYaW7+96d/ UXoFJS7pDKvEpBG8LGSiA6tqXjd2J10NqbM5pgoToldHQ/GB8xxNtwRIzJIlI8VOaRWg PpLyI0Zvqj7m4TDUuSnLung2/8f4A3dh6bMioWoxwO9cVgkLrtigEefD8MAPyAinB2h6 8vr8YU4+lFLV9u1HtS+JbOdzo4OZWplTIkmLBgb6Jucn1I4BLHFEhelqARSb++wkBNsp zX7LlBQ82X4t4LVNrY9SBTc9qHRaivZWxGv8wGlmYhoy8JyBr8CUvCAY/oi089IZ+XwA 4H0Q== X-Gm-Message-State: ALoCoQlFnBLGdxdZIjUGDya4kdhpBDVXHXpppX96pa340tfAqSGq5wuwbmb4GN9mMhTCN6Is290r X-Received: by 10.66.158.66 with SMTP id ws2mr15823366pab.37.1424967267880; Thu, 26 Feb 2015 08:14:27 -0800 (PST) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPSA id d11sm1490555pbu.10.2015.02.26.08.14.26 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Feb 2015 08:14:27 -0800 (PST) From: Mathieu Poirier To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, kaixu.xia@linaro.org Subject: [PATCH RESEND] coresight-stm: Bindings for System Trace Macrocell Date: Thu, 26 Feb 2015 09:14:18 -0700 Message-Id: <1424967258-28573-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. The driver has been posted here[1]. [1]. https://lkml.org/lkml/2015/2/25/743 Signed-off-by: Mathieu Poirier Acked-by: Rob Herring --- .../devicetree/bindings/arm/coresight.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..854127578718 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. @@ -31,6 +32,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properly for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-channel-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -198,3 +207,19 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-channel-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + };