From patchwork Wed Nov 19 23:15:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 412540 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D8880140147 for ; Thu, 20 Nov 2014 10:18:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933365AbaKSXR4 (ORCPT ); Wed, 19 Nov 2014 18:17:56 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:47463 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757131AbaKSXQT (ORCPT ); Wed, 19 Nov 2014 18:16:19 -0500 Received: by mail-wi0-f178.google.com with SMTP id hi2so3515054wib.17 for ; Wed, 19 Nov 2014 15:16:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=djq36YhWJKRGUJDV8SBRA4NE/4rBtYlgiEPsMi9Z0uo=; b=TyzkZDN7Suue7mrOZodyZhoArHxmui/msytKiyXKYFTEmfEnL5W30dNjHVxkWLTdq2 VTT8GgSXJ0QREfOzZUoer6ssIgCZcttBOv9izKGu1OajZSRz7DrMkvbyrNfXGMbGtmh4 gKv2obgWtVvr9Iw9XxWOiGteZ1x6EDf68WdXW383qe/Q8yYBkFaBPG6tAYtnGvsuZ3dt hTiuy1nyt79GDtb4CuZZPOQsDbamOzFV9caj6IOQvjVDfsbXBi1I44TAa5jZCtZyGqeS Cu42I0aaPZFZkdCOH4OOhiqyB3icDjFs9JvfMGKLhAZgDtLaVnyitdFKj79Vw4wN7iIj tfxw== X-Gm-Message-State: ALoCoQmUT/HNNO7Vt9sjKwYpnW5HoXpZWiLxOHFUmuxL52tBPDSW25sQVb+SSAH+hx/lKQh2pjFb X-Received: by 10.180.72.33 with SMTP id a1mr17528732wiv.18.1416438978294; Wed, 19 Nov 2014 15:16:18 -0800 (PST) Received: from radagast.localdomain (jahogan.plus.com. [212.159.75.221]) by mx.google.com with ESMTPSA id gi5sm797884wjd.26.2014.11.19.15.16.16 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Wed, 19 Nov 2014 15:16:17 -0800 (PST) From: James Hogan To: Mike Turquette , linux-metag@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: James Hogan , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH 11/15] dt: binding: add binding for TZ1090 PDC clock Date: Wed, 19 Nov 2014 23:15:39 +0000 Message-Id: <1416438943-11429-12-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1416438943-11429-1-git-send-email-james.hogan@imgtec.com> References: <1416438943-11429-1-git-send-email-james.hogan@imgtec.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TZ1090 PDC (PowerDown Controller) clock should be at 32.768KHz, and is generated either directly from the XTAL3 clock or by dividing the XTAL1 clock. Both the divide and the mux are in a single register which also contains GPIO output data, and may need to be used by other non-Linux cores and threads, so create a special clock binding for this clock. It essentially has just two clock inputs, and two clock outputs. Signed-off-by: James Hogan Cc: Mike Turquette Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: linux-metag@vger.kernel.org Cc: devicetree@vger.kernel.org --- .../bindings/clock/img,tz1090-pdc-clock.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt diff --git a/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt b/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt new file mode 100644 index 0000000..68e2eee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/img,tz1090-pdc-clock.txt @@ -0,0 +1,44 @@ +Binding for TZ1090 PDC clock. + +This binding uses the common clock binding[1]. It has two input clocks +(clocks[0..1]), two output clocks (out[0..1]), and a memory-mapped register +(reg) controlling a divider and a mux atomically with respect to other fields +and (non-Linux) threads or cores. + + _____ +clocks[0] ___| div |______________________ + |_____| | ____ out[0] + `--o| sw \__________ +clocks[1] ----------------|____/ out[1] + + +out[0] = clocks[0] / (reg[26:16] + 1) +out[1] = reg[30] ? clocks[1] : out[0] + + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "img,tz1090-pdc-clock". +- #clock-cells : from common clock binding; shall be set to 1. +- reg : base address for register controlling mux and divider +- clocks : clock specifiers of two parent clocks +- clock-output-names : from common clock binding. Name of two output clocks. + +Clock Specifier Definition: +- <1st-cell>: output clock number. + +Examples: + /* ___________ + * xtal1 ___| xtal1_div |____________________________ + * |___________| | ________ xtal1_div + * `--o| rtc_sw \____________ + * xtal3 ----------------------|________/ 32khz + */ + pdc_clk { + compatible = "img,tz1090-pdc-clock"; + #clock-cells = <1>; + reg = <0x02006500 4>; /* SOC_GPIO_CONTROL0 */ + clocks = <&xtal1>, <&xtal3>; + clock-output-names = "xtal1_div", "32khz"; + };