From patchwork Wed Aug 20 17:11:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 381742 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41DCE1400AB for ; Thu, 21 Aug 2014 03:12:03 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752432AbaHTRLx (ORCPT ); Wed, 20 Aug 2014 13:11:53 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:47799 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751516AbaHTRLw (ORCPT ); Wed, 20 Aug 2014 13:11:52 -0400 Received: by mail-pa0-f53.google.com with SMTP id rd3so12630262pab.12 for ; Wed, 20 Aug 2014 10:11:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Zax0n+enr39lh9x/Taahg2Wz2Y4vHJfE7iwUFBWGEoE=; b=gd0LyO9FPwEmtQiZVo5tdAhB8/g5aNl8TKIT4vuicyekKRCd3s0dqYa07JSkQchFN3 hKspDQ84qqf4OSRuLtOIg4OaWUPvPbnMbBpzTwLD63QZFA3FJ6kT9O4v3E90z7v7f89f 3STsRmbiIhG+S2R5vVLMZEAD3XMSoZLo0KCeU7e9sqy4wOayzoHQCP6GvTfXJmmfncyI 6oDTExFcbitI5+9xC4tmm/TQIeQ3chsi002hSvUzu6Waz4HiTg1kx72CfA0cUSN0HfCO qUz7PNECW5pi8dLkG9tv7wluSF6Hw8dpx3zNlVUSLFbS6DcoyrsMHCX2ouz+fCovq4C1 CSFg== X-Gm-Message-State: ALoCoQmeAoNd2MwdTt1PTmsKhvkesL0SI2Gk+Hh78MpEXa49cVcRf0l0LqTd56rdFz14gKctS8u2 X-Received: by 10.68.236.227 with SMTP id ux3mr29026108pbc.159.1408554712303; Wed, 20 Aug 2014 10:11:52 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPSA id pk15sm34878716pdb.49.2014.08.20.10.11.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Aug 2014 10:11:51 -0700 (PDT) From: mathieu.poirier@linaro.org To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org Subject: [PATCH v4] coresight: bindings for coresight drivers Date: Wed, 20 Aug 2014 11:11:38 -0600 Message-Id: <1408554698-24459-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pratik Patel Coresight IP blocks allow for the support of HW assisted tracing on ARM SoCs. Bindings for the currently available blocks are presented herein. Signed-off-by: Pratik Patel Signed-off-by: Panchaxari Prasannamurthy Signed-off-by: Mathieu Poirier --- .../devicetree/bindings/arm/coresight.txt | 205 +++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight.txt diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt new file mode 100644 index 0000000..2ee594d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -0,0 +1,205 @@ +* CoreSight Components + +CoreSight components are compliant with the ARM CoreSight architecture +specification and can be connected in various topologies to suit a particular +SoCs tracing needs. These trace components can generally be classified as sinks, +links and sources. Trace data produced by one or more sources flows through the +intermediate links connecting the source to the currently selected sink. Each +CoreSight component device should use these properties to describe its hardware +characteristcs. + +Required properties for all components *except* non-configurable replicators: + +- compatible : name of the component used for driver matching. Possible values +include: "arm,coresight-etb10", "arm,coresight-tpiu", "arm,coresight-tmc", +"arm,coresight-funnel", and "arm,coresight-etm3x". All of these have to +be supplemented with "arm,primecell" as drivers are using the AMBA bus +interface. Since non-configurable replicators don't show up on the AMBA +bus they don't need to be post-fixed with "arm,primecell". + +- reg : physical base address and length of the register set(s) of the component. + +- clocks : the clock associated to this component. + +- clock-names: the name of the clock as referenced by the code. Since we are +using the AMBA framework, the name should be "apb_pclk". + +- ports or port: The representation of the component's port layout using the +generic DT graph presentation found in "bindings/graph.txt". + +Non-configurable replicators: + +- compatible: currently supported value is "arm-replicator". Since non-configurable +replicators don't show up on the AMBA hey don't need to be post-fixed with +"arm,primecell". + +- id: a unique number that will identify this replicator. + +- ports or port: same as above. + +Optional properties for Sinks: + +- coresight-default-sink: must be specified for one of the sink devices that is +intended to be made the default sink. Other sink devices must not have this +specified. Not specifying this property on any of the sinks is invalid. + +Optional properties for ETM/PTMs: + +- arm,cp14: must be present if the system accesses ETM/PTM management registers +via co-processor 14. + +- arm,cp14: access to ETM/PTM management registers is made via cp14. + +- cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is +considered to belong to CPU0. + +Optional property for TMC: + +- arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router) + + +Example: + +1. Sinks + etb: etb@20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + coresight-default-sink; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etb_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + tpiu: tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + tpiu_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + +2. Links + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + /* this will show up in debugfs as "0.replicator" */ + id = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; + + funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel_out_port0: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + }; + }; + +3. Sources + ptm0: ptm@2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201c000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + + ptm1: ptm@2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201d000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + };