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From: Xiubo Li
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, Xiubo Li ,
Varka Bhadram
Subject: [PATCH 3/3] Document: fsl-sai: Adjust the document making it read
more comfortably.
Date: Tue, 19 Aug 2014 12:38:58 +0800
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Signed-off-by: Xiubo Li
Cc: Varka Bhadram
Reviewed-by: Varka Bhadram
---
.../devicetree/bindings/sound/fsl-sai.txt | 54 ++++++++++++----------
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index e25ef38..cd2930e 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -7,30 +7,34 @@ codec/DSP interfaces.
Required properties:
-- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
-- reg: Offset and length of the register set for the device.
-- clocks: Must contain an entry for each entry in clock-names.
+- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
+- reg: Offset and length of the register set for the device.
+- clocks: Must contain an entry for each entry in clock-names.
- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
- "mclk3" for bit clock and frame clock providing.
-- dmas : Generic dma devicetree binding as described in
- Documentation/devicetree/bindings/dma/dma.txt.
-- dma-names : Two dmas have to be defined, "tx" and "rx".
-- pinctrl-names: Must contain a "default" entry.
-- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
- See ../pinctrl/pinctrl-bindings.txt for details of the property values.
-- big-endian: Boolean property, required if all the SAI device registers
- are big-endian rather than little-endian.
-- msb-first: Configures whether the LSB or the MSB is transmitted first for
- the fifo data. If this property is absent, the LSB is transmitted first as
- default, or the MSB is transmitted first.
-- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
- that SAI will work in the synchronous mode (sync Tx with Rx) which means
- both the transimitter and receiver will send and receive data by following
- receiver's bit clocks and frame sync clocks.
-- fsl,sai-asynchronous: This is a boolean property. If present, indicating
- that SAI will work in the asynchronous mode, which means both transimitter
- and receiver will send and receive data by following their own bit clocks
- and frame sync clocks separately.
+ "mclk3" for bit clock and frame clock providing.
+- dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names : Two dmas have to be defined, "tx" and "rx".
+- pinctrl-names:Must contain a "default" entry.
+- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
+ See ../pinctrl/pinctrl-bindings.txt for details of the property
+ avalues.
+- big-endian: Boolean property, required if all the SAI device registers
+ are big-endian rather than little-endian.
+- msb-first: Configures whether the LSB or the MSB is transmitted first for
+ the fifo data. If this property is absent, the LSB is transmitted
+ first as default, or the MSB is transmitted first.
+- fsl,sai-synchronous-rx:
+ This is a boolean property. If present, indicating
+ that SAI will work in the synchronous mode (sync Tx with Rx)
+ which means both the transimitter and receiver will send and
+ receive data by following receiver's bit clocks and frame sync
+ clocks.
+- fsl,sai-asynchronous:
+ This is a boolean property. If present, indicating that SAI will
+ work in the asynchronous mode, which means both transimitter and
+ receiver will send and receive data by following their own bit
+ clocks and frame sync clocks separately.
Note:
- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
@@ -40,7 +44,7 @@ Note:
- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
Example:
-sai2: sai@40031000 {
+ sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
pinctrl-names = "default";
@@ -54,4 +58,4 @@ sai2: sai@40031000 {
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
big-endian;
msb-first;
-};
+ };