From patchwork Mon May 26 08:28:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 352413 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9A8981400A3 for ; Mon, 26 May 2014 18:31:24 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751782AbaEZIas (ORCPT ); Mon, 26 May 2014 04:30:48 -0400 Received: from mail-pb0-f53.google.com ([209.85.160.53]:46835 "EHLO mail-pb0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751719AbaEZIaq (ORCPT ); Mon, 26 May 2014 04:30:46 -0400 Received: by mail-pb0-f53.google.com with SMTP id md12so7367458pbc.40 for ; Mon, 26 May 2014 01:30:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eEEUQVof/QyfvrUzj3KXWjjDZ/ZZLMFtMbRxmJikMj8=; b=YSPZbIDD3cwBZXXaf3DLZ+tZFVAWItu96bRTgcwpGKS538YlggnTfX37XzzlxnK77f oO6imXT0i8kNZ0laYNSdsRJQkjj4K6sGm+pTsKX/LTIWnl15Ii+Tiy+nFtTYhDAtCHN/ OYKXmJuweeEj5ccsnuryZO7ZbgH36Kzzhd9sHCStKG7jGkk9Jlv2bfRq+QGqhEyB+pHd 4bF7ZFaf5zLHwVwu/B1iUEHhHMu/igCushLHx17U2YKkzpSk/QWPNHc3gK6PTAhki5VS IERjLSkT6LDoN+Lx+cmJSlYWgcwTQFNhDN2chI5jzs7vPxvre+Oy79DUg4P7cX7c5fXz a1xg== X-Gm-Message-State: ALoCoQmgkpTabGATz4h0LEqQU09WkvE3afIlMkepol96BkbB50AGyd0rH2ZffNJPqQb1dacMEDIC X-Received: by 10.66.190.167 with SMTP id gr7mr25444570pac.75.1401093046067; Mon, 26 May 2014 01:30:46 -0700 (PDT) Received: from linaro.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id dz4sm10690642pab.47.2014.05.26.01.30.42 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 26 May 2014 01:30:45 -0700 (PDT) From: Tushar Behera To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: tiwai@suse.de, perex@perex.cz, broonie@kernel.org, dianders@chromium.org, swarren@wwwdotorg.org Subject: [PATCH 2/2] ASoC: max98095: Add master clock handling Date: Mon, 26 May 2014 13:58:22 +0530 Message-Id: <1401092902-20525-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1401092902-20525-1-git-send-email-tushar.behera@linaro.org> References: <1401092902-20525-1-git-send-email-tushar.behera@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If master clock is provided through device tree, then update the master clock frequency during set_sysclk. Documentation has been updated to reflect the change. Signed-off-by: Tushar Behera --- .../devicetree/bindings/sound/max98095.txt | 6 +++++ sound/soc/codecs/max98095.c | 24 ++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/max98095.txt b/Documentation/devicetree/bindings/sound/max98095.txt index bacbeaa..318a4c8 100644 --- a/Documentation/devicetree/bindings/sound/max98095.txt +++ b/Documentation/devicetree/bindings/sound/max98095.txt @@ -8,6 +8,12 @@ Required properties: - reg : The I2C address of the device. +Optional properties: + +- clocks: The phandle of the master clock to the CODEC + +- clock-names: Should be "mclk" + Example: max98095: codec@11 { diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c index d6c1e4c..89ec004 100644 --- a/sound/soc/codecs/max98095.c +++ b/sound/soc/codecs/max98095.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,7 @@ struct max98095_priv { struct regmap *regmap; enum max98095_type devtype; struct max98095_pdata *pdata; + struct clk *mclk; unsigned int sysclk; struct max98095_cdata dai[3]; const char **eq_texts; @@ -1395,6 +1397,11 @@ static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, if (freq == max98095->sysclk) return 0; + if (!IS_ERR(max98095->mclk)) { + freq = clk_round_rate(max98095->mclk, freq); + clk_set_rate(max98095->mclk, freq); + } + /* Setup clocks for slave mode, and using the PLL * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) * 0x02 (when master clk is 20MHz to 40MHz).. @@ -1634,6 +1641,19 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec, break; case SND_SOC_BIAS_PREPARE: + /* + * SND_SOC_BIAS_PREPARE is called while preparing for a + * transition to ON or away from ON. If current bias_level + * is SND_SOC_BIAS_ON, then it is preparing for a transition + * away from ON. Disable the clock in that case, otherwise + * enable it. + */ + if (!IS_ERR(max98095->mclk)) { + if (codec->dapm.bias_level == SND_SOC_BIAS_ON) + clk_disable_unprepare(max98095->mclk); + else + clk_prepare_enable(max98095->mclk); + } break; case SND_SOC_BIAS_STANDBY: @@ -2238,6 +2258,10 @@ static int max98095_probe(struct snd_soc_codec *codec) struct i2c_client *client; int ret = 0; + max98095->mclk = devm_clk_get(codec->dev, "mclk"); + if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* reset the codec, the DSP core, and disable all interrupts */ max98095_reset(codec);