From patchwork Tue May 13 10:10:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 348325 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43D95140087 for ; Tue, 13 May 2014 20:20:55 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759424AbaEMKUx (ORCPT ); Tue, 13 May 2014 06:20:53 -0400 Received: from top.free-electrons.com ([176.31.233.9]:37561 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1759367AbaEMKUu (ORCPT ); Tue, 13 May 2014 06:20:50 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id A5E23A9C; Tue, 13 May 2014 12:20:49 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5FFB8170B; Tue, 13 May 2014 12:10:43 +0200 (CEST) From: Thomas Petazzoni To: Russell King , Will Deacon , Catalin Marinas , devicetree@vger.kernel.org, Grant Likely , Rob Herring Cc: Albin Tonnerre , linux-arm-kernel@lists.infradead.org, Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia Subject: [PATCHv2 3/4] ARM: mm: add support for HW coherent systems in PL310 Date: Tue, 13 May 2014 12:10:38 +0200 Message-Id: <1399975839-5311-4-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1399975839-5311-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1399975839-5311-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a separate 'arm,pl310-coherent-cache' compatible string, which identifies a PL310 cache in an I/O coherent configuration. This compatible string is associated with a different set of l2x0_of_data, in which the ->sync operation is NULL. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Signed-off-by: Thomas Petazzoni --- Documentation/devicetree/bindings/arm/l2cc.txt | 2 ++ arch/arm/mm/cache-l2x0.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index b513cb8..41953b3 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -8,6 +8,8 @@ Required properties: - compatible : should be one of: "arm,pl310-cache" + "arm,pl310-coherent-cache", used for I/O coherent platforms using + the PL310 cache "arm,l220-cache" "arm,l210-cache" "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 7abde2ce..ae19540 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -889,6 +889,26 @@ static const struct l2x0_of_data pl310_data = { }, }; +/* + * PL310 operations used on I/O coherent systems. Theoretically, no + * outer cache operations would be needed, except that for secondary + * processors bring up, a few cache maintenance operations are needed + * because secondary processors are not directly coherent with the L2 + * cache when they start up. + */ +static const struct l2x0_of_data pl310_coherent_data = { + .setup = pl310_of_setup, + .save = pl310_save, + .outer_cache = { + .resume = pl310_resume, + .inv_range = l2x0_inv_range, + .clean_range = l2x0_clean_range, + .flush_range = l2x0_flush_range, + .flush_all = l2x0_flush_all, + .inv_all = l2x0_inv_all, + }, +}; + static const struct l2x0_of_data l2x0_data = { .setup = l2x0_of_setup, .save = NULL, @@ -955,6 +975,7 @@ static const struct of_device_id l2x0_ids[] __initconst = { { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data }, { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, + { .compatible = "arm,pl310-coherent-cache", .data = (void *)&pl310_coherent_data }, { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */ .data = (void *)&bcm_l2x0_data}, { .compatible = "brcm,bcm11351-a2-pl310-cache",