From patchwork Tue Apr 29 02:18:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiubo Li X-Patchwork-Id: 343648 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D6566140079 for ; Tue, 29 Apr 2014 13:04:25 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752099AbaD2DDe (ORCPT ); Mon, 28 Apr 2014 23:03:34 -0400 Received: from mail-bn1lp0140.outbound.protection.outlook.com ([207.46.163.140]:41268 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752048AbaD2DDc (ORCPT ); Mon, 28 Apr 2014 23:03:32 -0400 Received: from BY2PR03CA041.namprd03.prod.outlook.com (10.141.249.14) by BY2PR03MB505.namprd03.prod.outlook.com (10.141.143.12) with Microsoft SMTP Server (TLS) id 15.0.921.12; Tue, 29 Apr 2014 03:03:30 +0000 Received: from BL2FFO11FD046.protection.gbl (2a01:111:f400:7c09::121) by BY2PR03CA041.outlook.office365.com (2a01:111:e400:2c5d::14) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Tue, 29 Apr 2014 03:03:29 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.1) by BL2FFO11FD046.mail.protection.outlook.com (10.173.161.208) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Tue, 29 Apr 2014 03:03:29 +0000 Received: from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s3T33Mo6016875; Mon, 28 Apr 2014 20:03:26 -0700 From: Xiubo Li To: , , CC: , , , Xiubo Li , Jingchang Lu Subject: [PATCHv3 1/3] clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation Date: Tue, 29 Apr 2014 10:18:57 +0800 Message-ID: <1398737939-5334-2-git-send-email-Li.Xiubo@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1398737939-5334-1-git-send-email-Li.Xiubo@freescale.com> References: <1398737939-5334-1-git-send-email-Li.Xiubo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.1; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(81542001)(83072002)(50986999)(31966008)(20776003)(81342001)(77982001)(80976001)(86362001)(101416001)(36756003)(74502001)(47776003)(76176999)(62966002)(87936001)(48376002)(46102001)(44976005)(80022001)(50226001)(83322001)(19580395003)(77096999)(6806004)(85852003)(88136002)(92726001)(4396001)(99396002)(77156001)(93916002)(92566001)(76482001)(50466002)(87286001)(79102001)(19580405001)(89996001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR03MB505; H:tx30smr01.am.freescale.net; FPR:FA21FBFE.2D14D461.AF99F33.80DEF24B.2024A; MLV:sfv; PTR:gate-tx3.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 0196A226D1 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The FTM binding could be used on Vybrid and LS1+, add a binding document for it. Signed-off-by: Xiubo Li Cc: Shawn Guo Cc: Jingchang Lu --- .../devicetree/bindings/timer/fsl,ftm-timer.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt new file mode 100644 index 0000000..aa8c402 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt @@ -0,0 +1,31 @@ +Freescale FlexTimer Module (FTM) Timer + +Required properties: + +- compatible : should be "fsl,ftm-timer" +- reg : Specifies base physical address and size of the register sets for the + clock event device and clock source device. +- interrupts : Should be the clock event device interrupt. +- clocks : The clocks provided by the SoC to drive the timer, must contain an + entry for each entry in clock-names. +- clock-names : Must include the following entries: + o "ftm-evt" + o "ftm-src" + o "ftm-evt-counter-en" + o "ftm-src-counter-en" +- big-endian: One boolean property, the big endian mode will be in use if it is + present, or the little endian mode will be in use for all the device registers. + +Example: +ftm: ftm@400b8000 { + compatible = "fsl,ftm-timer"; + reg = <0x400b8000 0x1000 0x400b9000 0x1000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm-evt", "ftm-src", + "ftm-evt-counter-en", "ftm-src-counter-en"; + clocks = <&clks VF610_CLK_FTM2>, + <&clks VF610_CLK_FTM3>, + <&clks VF610_CLK_FTM2_EXT_FIX_EN>, + <&clks VF610_CLK_FTM3_EXT_FIX_EN>; + big-endian; +};