From patchwork Mon Apr 28 03:53:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 343228 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0CDB01400A9 for ; Mon, 28 Apr 2014 14:52:19 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751964AbaD1EwS (ORCPT ); Mon, 28 Apr 2014 00:52:18 -0400 Received: from dns-bn1lp0143.outbound.protection.outlook.com ([207.46.163.143]:26743 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751592AbaD1EwR (ORCPT ); Mon, 28 Apr 2014 00:52:17 -0400 Received: from BLUPR03CA035.namprd03.prod.outlook.com (10.141.30.28) by BLUPR03MB421.namprd03.prod.outlook.com (10.141.78.140) with Microsoft SMTP Server (TLS) id 15.0.929.12; Mon, 28 Apr 2014 04:52:15 +0000 Received: from BL2FFO11FD056.protection.gbl (2a01:111:f400:7c09::110) by BLUPR03CA035.outlook.office365.com (2a01:111:e400:879::28) with Microsoft SMTP Server (TLS) id 15.0.934.12 via Frontend Transport; Mon, 28 Apr 2014 04:52:15 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BL2FFO11FD056.mail.protection.outlook.com (10.173.161.184) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 28 Apr 2014 04:52:15 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3S4pr3Y009014; Sun, 27 Apr 2014 21:52:11 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v2 04/10] Documentation: mtd: add a new document for SPI NOR flash Date: Mon, 28 Apr 2014 11:53:41 +0800 Message-ID: <1398657227-20721-5-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com> References: <1398657227-20721-1-git-send-email-b32955@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(74502001)(50466002)(50226001)(31966008)(79102001)(89996001)(46102001)(19580395003)(19580405001)(87286001)(81342001)(36756003)(77156001)(62966002)(48376002)(93916002)(80976001)(74662001)(88136002)(81542001)(20776003)(44976005)(33646001)(83322001)(80022001)(6806004)(77096999)(4396001)(99396002)(92726001)(77982001)(47776003)(92566001)(85852003)(83072002)(76482001)(87936001)(76176999)(42262001)(217873001); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB421; H:az84smr01.freescale.net; FPR:793C44DC.2F35C428.DBF78B20.80DAB6B9.20193; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01952C6E96 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We need a DT property to store the dummy cycles for DDR Quad read. This is a common feature for the SPI NOR flash, such as Spansion and Micron chips. Add this file to describe this specific SPI NOR flash features which will be referred by the SPI NOR flash drivers. Signed-off-by: Huang Shijie --- .../devicetree/bindings/mtd/spi-nor-flash.txt | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/spi-nor-flash.txt diff --git a/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt new file mode 100644 index 0000000..aba4d54 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt @@ -0,0 +1,7 @@ +This file defines some DT properties for specific SPI NOR flash features. +The SPI NOR controller drivers may refer to this file, such as fsl-quadspi.txt + +Optional properties: + - spi-nor,ddr-quad-read-dummy: The dummy cycles used by the DDR Quad read. + Please refer to the chip's datasheet. This + property can be 4 or 6 which is less then 8.