From patchwork Wed Apr 23 10:16:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 341777 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 652B2140195 for ; Wed, 23 Apr 2014 21:14:47 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751860AbaDWLOf (ORCPT ); Wed, 23 Apr 2014 07:14:35 -0400 Received: from mail-bl2lp0204.outbound.protection.outlook.com ([207.46.163.204]:29534 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752390AbaDWLOa (ORCPT ); Wed, 23 Apr 2014 07:14:30 -0400 Received: from BL2PR03CA018.namprd03.prod.outlook.com (10.141.66.26) by BL2PR03MB417.namprd03.prod.outlook.com (10.141.92.12) with Microsoft SMTP Server (TLS) id 15.0.921.12; Wed, 23 Apr 2014 11:14:16 +0000 Received: from BN1BFFO11FD003.protection.gbl (2a01:111:f400:7c10::1:149) by BL2PR03CA018.outlook.office365.com (2a01:111:e400:c1b::26) with Microsoft SMTP Server (TLS) id 15.0.921.12 via Frontend Transport; Wed, 23 Apr 2014 11:14:15 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BN1BFFO11FD003.mail.protection.outlook.com (10.58.144.66) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Wed, 23 Apr 2014 11:14:15 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3NBDxmX008408; Wed, 23 Apr 2014 04:14:12 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v1 4/7] Documentation: fsl-quadspi: update the document Date: Wed, 23 Apr 2014 18:16:52 +0800 Message-ID: <1398248215-26768-5-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: References: X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(47776003)(20776003)(81342001)(62966002)(11926002)(50466002)(93916002)(77096999)(74502001)(74662001)(80022001)(77156001)(48376002)(79102001)(31966008)(81542001)(76176999)(50986999)(99396002)(36756003)(89996001)(44976005)(88136002)(33646001)(76482001)(46102001)(92726001)(92566001)(83322001)(19580395003)(87936001)(19580405001)(50226001)(83072002)(6806004)(77982001)(87286001)(4396001)(85852003)(80976001)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB417; H:az84smr01.freescale.net; FPR:FCF1F45C.859605D3.7BE474F2.80D9DEB1.20229; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01901B3451 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The patch updates the document by adding more information to describe the DT proporties used by the Freescale Quadspi driver and the childs nodes. For the child node for SPI NOR flash, we add the required property ("spi-max-frequency"), and refer to spi-nor-flash.txt for the optional properties. Signed-off-by: Huang Shijie --- .../devicetree/bindings/mtd/fsl-quadspi.txt | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt index 823d134..7e1dbaf 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt @@ -1,5 +1,11 @@ * Freescale Quad Serial Peripheral Interface(QuadSPI) +The QuadSPI controller acts as the SPI master. It is described with a node +for the controller and a set of child nodes for each SPI NOR flash. + +Part I - The DT node for the controller: +------------------------------ + Required properties: - compatible : Should be "fsl,vf610-qspi" - reg : the first contains the register location and length, @@ -18,6 +24,16 @@ Optional properties: bus, you should enable this property. (Please check the board's schematic.) +Part II - The DT nodes for each SPI NOR flash +------------------------------ +Required properties: +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt + If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR + quad read feature for the driver. + Example: qspi0: quadspi@40044000 {