From patchwork Thu Apr 17 05:59:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiubo Li X-Patchwork-Id: 339787 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 67A6414007D for ; Thu, 17 Apr 2014 16:43:41 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751090AbaDQGmt (ORCPT ); Thu, 17 Apr 2014 02:42:49 -0400 Received: from ch1ehsobe004.messaging.microsoft.com ([216.32.181.184]:4170 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750986AbaDQGms (ORCPT ); Thu, 17 Apr 2014 02:42:48 -0400 Received: from mail220-ch1-R.bigfish.com (10.43.68.245) by CH1EHSOBE004.bigfish.com (10.43.70.54) with Microsoft SMTP Server id 14.1.225.22; Thu, 17 Apr 2014 06:42:04 +0000 Received: from mail220-ch1 (localhost [127.0.0.1]) by mail220-ch1-R.bigfish.com (Postfix) with ESMTP id 6B171320546; Thu, 17 Apr 2014 06:42:04 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6h208chzz1de098h8275bh8275dh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh26d3h1155h) Received: from mail220-ch1 (localhost.localdomain [127.0.0.1]) by mail220-ch1 (MessageSwitch) id 1397716923340486_22543; Thu, 17 Apr 2014 06:42:03 +0000 (UTC) Received: from CH1EHSMHS008.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.238]) by mail220-ch1.bigfish.com (Postfix) with ESMTP id 4CEF13A0050; Thu, 17 Apr 2014 06:42:03 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS008.bigfish.com (10.43.70.8) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 17 Apr 2014 06:42:03 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.174.2; Thu, 17 Apr 2014 06:42:45 +0000 Received: from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3H6gbIv023457; Wed, 16 Apr 2014 23:42:37 -0700 From: Xiubo Li To: , , , , , , , CC: , , , Xiubo Li , Shawn Guo , Jingchang Lu Subject: [PATCH] clocksource: pit: Add Freescale PIT-RTI devicetree Documentation Date: Thu, 17 Apr 2014 13:59:49 +0800 Message-ID: <1397714389-10263-1-git-send-email-Li.Xiubo@freescale.com> X-Mailer: git-send-email 1.8.0 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add Freescale Periodic Interrupt Timer (PIT-RTI) devicetree Documentation, The PIT-RTI binding has already been used on Vybrid, so this add a binding document for it. Signed-off-by: Xiubo Li Cc: Shawn Guo Cc: Jingchang Lu --- .../devicetree/bindings/timer/fsl,vf610-pit.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/fsl,vf610-pit.txt diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.txt b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.txt new file mode 100644 index 0000000..67df182 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.txt @@ -0,0 +1,21 @@ +Freescale Periodic Interrupt Timer (PIT-RTI) + +Required properties: + +- compatible : should be "fsl,vf610-pit" +- reg : Specifies base physical address and size of the register set for the + clock event device and clock source device. +- interrupts : Should be the clock event device interrupt. +- clocks : The clocks provided by the SoC to drive the timer, must contain an + entry for each entry in clock-names. +- clock-names : Must include the "pit" entry. + +Example: + +pit: pit@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; +};