From patchwork Fri Mar 28 17:59:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 334840 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6A0C7140079 for ; Sat, 29 Mar 2014 05:02:37 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752983AbaC1SCL (ORCPT ); Fri, 28 Mar 2014 14:02:11 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:34887 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754239AbaC1R7j (ORCPT ); Fri, 28 Mar 2014 13:59:39 -0400 Received: by mail-wi0-f169.google.com with SMTP id hm4so1013995wib.2 for ; Fri, 28 Mar 2014 10:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VI4smFQF7ByDqK5actamsU5wsv3E9MeP4diyd2NH22A=; b=Oem/giu6sr1H7zcY1oTL+ZV+wiQe/wcWEGEjn2/n4+gsS/7ZD14dQt8hMlQd5Bzz1v mlcO5gquJXXt18eZZZiUv1nCphutqVKkLC0eJMQjw61lZ2+iNHFFS3ErdHDUEs5M76pz stuBbu7hrY4H3mXLrJw44aotwpexm+wAkdnl750+VnxqhcZAZZXRuVITATwmqd7Nhtka GqOZuX3amL5iCoTvpwkv+3oa8SmwEwFQDZE2tA71TbsA+pJVfoflx1zsZHX0WW9+hlwS TUnRoDktGrwcY1aeXQRedBuajuQ25Jb5EY4+PhFhiscj4RcSg6G8sfJzRShcdHY69NER plmw== X-Received: by 10.180.149.143 with SMTP id ua15mr14099827wib.36.1396029577603; Fri, 28 Mar 2014 10:59:37 -0700 (PDT) Received: from localhost.localdomain (col31-4-88-188-80-5.fbx.proxad.net. [88.188.80.5]) by mx.google.com with ESMTPSA id mw3sm9217422wic.7.2014.03.28.10.59.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Mar 2014 10:59:36 -0700 (PDT) From: Boris BREZILLON To: Rob Landley , Nicolas Ferre , Jean-Christophe Plagniol-Villard , Thomas Gleixner Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Boris BREZILLON Subject: [RFC PATCH v2 07/10] irqchip: atmel-aic: document new dt properties and children nodes Date: Fri, 28 Mar 2014 18:59:05 +0100 Message-Id: <1396029548-10928-8-git-send-email-b.brezillon.dev@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396029548-10928-1-git-send-email-b.brezillon.dev@gmail.com> References: <1396029548-10928-1-git-send-email-b.brezillon.dev@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add irq muxing and irq-mapping dt bindings documentation. Signed-off-by: Boris BREZILLON --- .../bindings/interrupt-controller/atmel,aic.txt | 42 +++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 2742e9c..d46ec8e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -18,8 +18,33 @@ Required properties: The third cell is used to specify the irq priority from 0 (lowest) to 7 (highest). - reg: Should contain AIC registers location and length +- #address-cells: Shall be 2. The first cell encodes the irq line (or irq id). + The second cell encodes the register offset within the iomem range. +- #size-cells: Shall be 1. +- ranges: Defines the iomem ranges attached to a given irq line (e.i. irq + line 1 <=> SYSC range). - atmel,external-irqs: u32 array of external irqs. +Optional properties: +- atmel,irq-mapping: u32 mask array representing the available irqs: + e.i. : atmel,irq-mapping = <0xffff1fff> => irqs 13 to 15 are unavailables + +Optional children nodes: +- muxed irq entries: + Required properties: + * compatible: Shall be + "atmel,aic-mux-1reg-irq": irq enable/disable/retrieve-status is done by + setting/clearing/reading flags in a specific register + or + "atmel,aic-mux-3reg-irq": irq enable/disable/retrieve-status is done + by writing/reading flags in specific enable/disable/mask registers + * reg: encode the interrupt control register. + The first cell encode the irq line. + The second cell encode the offset register within its iomem range + The last cell encode the iomem region size (should always be set to 0x4). + * atmel,aic-mux-reg-mask: define the mask used to disable the interrupts + generated by the muxed entry. + Examples: /* * AIC @@ -29,11 +54,26 @@ Examples: interrupt-controller; interrupt-parent; #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <1>; reg = <0xfffff000 0x200>; + ranges = <0x1 0x0 0xffffc000 0x4000>; + + dbgu_irq: irq@1,320c { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <1 0x320c 0x4>; + atmel,aic-mux-reg-mask = <0xc0001afb>; + }; + + pmc_irq: irq@1,3c64 { + compatible = "atmel,aic-mux-3reg-irq"; + reg = <1 0x3c64 0x4>; + atmel,aic-mux-reg-mask = <0xf0f>; + }; }; /* - * An interrupt generating device that is wired to an AIC. + * A device generating interrupts wired to the AIC. */ dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma";