From patchwork Wed Mar 12 18:07:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 329608 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C67E42C00B5 for ; Thu, 13 Mar 2014 05:09:59 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756249AbaCLSIB (ORCPT ); Wed, 12 Mar 2014 14:08:01 -0400 Received: from mail-wg0-f46.google.com ([74.125.82.46]:32849 "EHLO mail-wg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756194AbaCLSH6 (ORCPT ); Wed, 12 Mar 2014 14:07:58 -0400 Received: by mail-wg0-f46.google.com with SMTP id b13so5634004wgh.29 for ; Wed, 12 Mar 2014 11:07:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bxAZOx+zMXvIte47ecdAsMtpV3u+tk7vCvjn1oAs2/0=; b=q2q2V4mY6g+curBGLKMwy8NKuM+4jpAzmc4QQTgM24jbiWxTXpsAGj594E+ElTvfbj 5909rlqPcNWwoxTtSKjHCKhDUMsUlXhFClSm4HQU88if1nQcxpyRNTOxT+LodwH+kRNi ahwpa4oaS49uOc0KhEH04OfotnDJeVwGwJQb/fzLCa4fSmx1KrS+8vKyC8esxkHm0DoU yELSAqhbHFaAxxzfKMxtbTztnOy1SdcOWzVHxF3qyjzCt4rupbGvnmjnpnfZW2MqFo5B w13vyfOUlhLC/BggwnF14IA4DZ86QQq3oMEPvps7d4i+UzaW3FyETtLX7OEmlg4BAcd2 whBA== X-Received: by 10.180.92.196 with SMTP id co4mr4591919wib.50.1394647677207; Wed, 12 Mar 2014 11:07:57 -0700 (PDT) Received: from localhost.localdomain (col31-4-88-188-80-5.fbx.proxad.net. [88.188.80.5]) by mx.google.com with ESMTPSA id bj3sm71576119wjb.14.2014.03.12.11.07.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 12 Mar 2014 11:07:56 -0700 (PDT) From: Boris BREZILLON To: Maxime Ripard , Rob Herring , David Woodhouse , Grant Likely , Brian Norris , Jason Gunthorpe , Arnd Bergmann Cc: Boris BREZILLON , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, dev@linux-sunxi.org Subject: [PATCH v3 4/9] of: mtd: add documentation for the ONFI NAND timing mode property Date: Wed, 12 Mar 2014 19:07:39 +0100 Message-Id: <1394647664-8258-5-git-send-email-b.brezillon.dev@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1394647664-8258-1-git-send-email-b.brezillon.dev@gmail.com> References: <1394647664-8258-1-git-send-email-b.brezillon.dev@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the ONFI NAND timing mode property. Signed-off-by: Boris BREZILLON --- Documentation/devicetree/bindings/mtd/nand.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt index b53f92e..2046027 100644 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ b/Documentation/devicetree/bindings/mtd/nand.txt @@ -19,3 +19,11 @@ errors per {size} bytes". The interpretation of these parameters is implementation-defined, so not all implementations must support all possible combinations. However, implementations are encouraged to further specify the value(s) they support. + +- onfi,nand-timing-mode: an integer encoding the supported ONFI timing modes of + the NAND chip. Each supported mode is represented as a bit position (i.e. : + mode 0 and 1 => (1 << 0) | (1 << 1) = 0x3). + This is only used when the chip does not support the ONFI standard. + The last bit set represent the closest mode fulfilling the NAND chip timings. + For a full description of the different timing modes see this document: + www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf