From patchwork Sat Feb 22 19:14:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 323233 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2CEF42C0257 for ; Sun, 23 Feb 2014 06:16:25 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751484AbaBVTQZ (ORCPT ); Sat, 22 Feb 2014 14:16:25 -0500 Received: from vps0.lunn.ch ([178.209.37.122]:33246 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751300AbaBVTQY (ORCPT ); Sat, 22 Feb 2014 14:16:24 -0500 Received: from lunn by vps0.lunn.ch with local (Exim 4.80) (envelope-from ) id 1WHI2i-00036l-Eu; Sat, 22 Feb 2014 20:15:20 +0100 From: Andrew Lunn To: Jason Cooper , Sebastian Hesselbarth , Gregory Clement Cc: linux ARM , Andrew Lunn , devicetree@vger.kernel.org Subject: [PATCH v4 10/22] ARM: MM: Add DT binding for Feroceon L2 cache Date: Sat, 22 Feb 2014 20:14:52 +0100 Message-Id: <1393096504-11844-11-git-send-email-andrew@lunn.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1393096504-11844-1-git-send-email-andrew@lunn.ch> References: <1393096504-11844-1-git-send-email-andrew@lunn.ch> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn Tested-by: Jason Gunthorpe cc: devicetree@vger.kernel.org --- v2: Change compatible strings to follow l2x0 convention Only expect register for kirkwood-cache. Default to write through if no DT node. Rename writethrough to wt-override to follow l2cc binding. Split kirkwood.dtsi change into a patch of its own. v3 Remove wt-override from the binding Respect CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH --- .../devicetree/bindings/arm/mrvl/feroceon.txt | 16 ++++++++ arch/arm/include/asm/hardware/cache-feroceon-l2.h | 2 + arch/arm/mach-kirkwood/board-dt.c | 18 ++------- arch/arm/mm/cache-feroceon-l2.c | 43 ++++++++++++++++++++++ 4 files changed, 64 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 8edd330aabf6..12e1588dc4f1 100644 --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 29c246858d5a..ec0702c02d6c 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void) iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); } -static void __init kirkwood_l2_init(void) -{ -#ifdef CONFIG_CACHE_FEROCEON_L2 -#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH - writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(1); -#else - writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); - feroceon_l2_init(0); -#endif -#endif -} - static struct resource kirkwood_cpufreq_resources[] = { [0] = { .start = CPU_CONTROL_PHYS, @@ -211,8 +198,9 @@ static void __init kirkwood_dt_init(void) BUG_ON(mvebu_mbus_dt_init()); - kirkwood_l2_init(); - +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_of_init(); +#endif kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 898362e7972b..8dc1a2b5a8ed 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -13,11 +13,16 @@ */ #include +#include +#include #include +#include #include #include #include +#define L2_WRITETHROUGH_KIRKWOOD BIT(4) + /* * Low-level cache maintenance operations. * @@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override) printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", l2_wt_override ? ", in WT override mode" : ""); } +#ifdef CONFIG_OF +static const struct of_device_id feroceon_ids[] __initconst = { + { .compatible = "marvell,kirkwood-cache"}, + { .compatible = "marvell,feroceon-cache"}, + {} +}; + +int __init feroceon_of_init(void) +{ + struct device_node *node; + void __iomem *base; + bool l2_wt_override = false; + struct resource res; + +#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) + l2_wt_override = true; +#endif + + node = of_find_matching_node(NULL, feroceon_ids); + if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { + if (of_address_to_resource(node, 0, &res)) + return -ENODEV; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -ENOMEM; + + if (l2_wt_override) + writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); + else + writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); + } + + feroceon_l2_init(l2_wt_override); + + return 0; +} +#endif