From patchwork Mon Feb 17 19:55:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dinguyen@altera.com X-Patchwork-Id: 321125 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 69CD92C00C1 for ; Tue, 18 Feb 2014 06:57:24 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754408AbaBQT5X (ORCPT ); Mon, 17 Feb 2014 14:57:23 -0500 Received: from na01-by2-obe.ptr.protection.outlook.com ([207.46.100.31]:3975 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753222AbaBQT5W (ORCPT ); Mon, 17 Feb 2014 14:57:22 -0500 Received: from BN1AFFO11FD026.protection.gbl (10.58.52.30) by BN1AFFO11HUB028.protection.gbl (10.58.52.138) with Microsoft SMTP Server (TLS) id 15.0.868.13; Mon, 17 Feb 2014 19:57:19 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BN1AFFO11FD026.mail.protection.outlook.com (10.58.52.86) with Microsoft SMTP Server (TLS) id 15.0.868.13 via Frontend Transport; Mon, 17 Feb 2014 19:57:19 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.342.0; Mon, 17 Feb 2014 11:44:41 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s1HJvE5B027229; Mon, 17 Feb 2014 11:57:17 -0800 (PST) From: To: CC: , , Dinh Nguyen , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Seungwon Jeon , Jaehoon Chung , Chris Ball Subject: [PATCHv2 3/3] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform Date: Mon, 17 Feb 2014 13:55:11 -0600 Message-ID: <1392666911-15985-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392666911-15985-1-git-send-email-dinguyen@altera.com> References: <1392666911-15985-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(189002)(199002)(87266001)(87286001)(80022001)(65816001)(85306002)(95666001)(47736001)(33646001)(47446002)(50466002)(92566001)(31966008)(74662001)(83072002)(85852003)(81542001)(69226001)(92726001)(74366001)(81342001)(86152002)(90146001)(89996001)(94946001)(48376002)(56816005)(74502001)(93136001)(94316002)(4396001)(62966002)(87936001)(47976001)(49866001)(50986001)(50226001)(95416001)(53806001)(54316002)(47776003)(79102001)(36756003)(83322001)(20776003)(88136002)(74706001)(74876001)(81686001)(77982001)(93916002)(575784001)(93516002)(86362001)(80976001)(46102001)(81816001)(51856001)(59766001)(56776001)(19580395003)(76482001)(19580405001)(53416003)(77156001)(44976005)(76796001)(63696002)(6806004)(77096001)(76786001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1AFFO11HUB028; H:SJ-ITEXEDGE02.altera.priv.altera.com; CLIP:66.35.236.232; FPR:BE14FCEE.88D79495.357B9F33.CE46209.20421; MLV:nspm; InfoDomainNonexistentMX:1; A:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 012570D5A0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dinh Nguyen Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform specific implementation of the dwc_mmc driver. Also add the "syscon" binding to the "altr,sys-mgr" node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock phase shift settings. Finally, fix an indentation error for the sysmgr node. Signed-off-by: Dinh Nguyen Acked-by: Steffen Trumtrar Tested-by: Steffen Trumtrar Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Seungwon Jeon Cc: Jaehoon Chung Cc: Chris Ball --- v2: Fix indentation for the sysmgr node --- .../devicetree/bindings/mmc/socfpga-dw-mshc.txt | 23 ++++++++++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 15 +++++++++++-- arch/arm/boot/dts/socfpga_arria5.dtsi | 11 ++++++++++ arch/arm/boot/dts/socfpga_cyclone5.dtsi | 11 ++++++++++ arch/arm/boot/dts/socfpga_vt.dts | 11 ++++++++++ 5 files changed, 69 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt new file mode 100644 index 0000000..4897bea --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt @@ -0,0 +1,23 @@ +* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be + - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform + +Example: + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 129 4>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 3d62f47..eee73c9 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -474,6 +474,17 @@ arm,data-latency = <2 1 1>; }; + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; @@ -528,8 +539,8 @@ }; sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x4000>; + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; }; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index a85b404..6c87b70 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -27,6 +27,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + serial0@ffc02000 { clock-frequency = <100000000>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index a8716f6..ca41b0e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,6 +28,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index d1ec0ca..222313f 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -41,6 +41,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff700000 { phy-mode = "gmii"; status = "okay";