From patchwork Mon Feb 17 07:30:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dinguyen@altera.com X-Patchwork-Id: 320865 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1C09B2C008F for ; Mon, 17 Feb 2014 18:33:22 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751016AbaBQHdH (ORCPT ); Mon, 17 Feb 2014 02:33:07 -0500 Received: from mail-bn1bhn0126.outbound.protection.outlook.com ([157.56.111.126]:48669 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750926AbaBQHdE (ORCPT ); Mon, 17 Feb 2014 02:33:04 -0500 Received: from BY2FFO11FD023.protection.gbl (10.1.14.33) by BY2FFO11HUB064.protection.gbl (10.1.15.239) with Microsoft SMTP Server (TLS) id 15.0.868.13; Mon, 17 Feb 2014 07:33:01 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BY2FFO11FD023.mail.protection.outlook.com (10.1.15.212) with Microsoft SMTP Server (TLS) id 15.0.868.13 via Frontend Transport; Mon, 17 Feb 2014 07:33:01 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.342.0; Sun, 16 Feb 2014 23:20:23 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s1H7WuqS010933; Sun, 16 Feb 2014 23:32:58 -0800 (PST) From: To: CC: , , Dinh Nguyen , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Seungwon Jeon" , Jaehoon Chung , "Chris Ball" Subject: [PATCH 3/3] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform Date: Mon, 17 Feb 2014 01:30:44 -0600 Message-ID: <1392622244-18015-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392622244-18015-1-git-send-email-dinguyen@altera.com> References: <1392622244-18015-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(189002)(199002)(44976005)(74876001)(6806004)(93916002)(81542001)(79102001)(56776001)(77096001)(74502001)(31966008)(47776003)(95416001)(76482001)(74662001)(80976001)(77982001)(77156001)(80022001)(83322001)(94946001)(19580405001)(19580395003)(47446002)(74706001)(48376002)(50466002)(69226001)(95666001)(36756003)(53806001)(81342001)(74366001)(81686001)(76786001)(20776003)(63696002)(94316002)(54316002)(76796001)(81816001)(59766001)(90146001)(83072002)(85852003)(56816005)(575784001)(4396001)(86362001)(33646001)(92726001)(51856001)(93516002)(53416003)(85306002)(46102001)(65816001)(86152002)(92566001)(49866001)(47736001)(47976001)(87266001)(87936001)(50986001)(50226001)(89996001)(62966002)(87286001)(93136001)(88136002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2FFO11HUB064; H:SJ-ITEXEDGE02.altera.priv.altera.com; CLIP:66.35.236.232; FPR:BA14FCEE.88D79425.347BAF03.D46E39.203EB; MLV:nspm; InfoDomainNonexistentMX:1; A:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 012570D5A0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dinh Nguyen Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform specific implementation of the dwc_mmc driver. Also add the "syscon" binding to the "altr,sys-mgr" node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock phase shift settings. Signed-off-by: Dinh Nguyen Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Seungwon Jeon Cc: Jaehoon Chung Cc: Chris Ball --- .../devicetree/bindings/mmc/socfpga-dw-mshc.txt | 23 ++++++++++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 13 ++++++++++- arch/arm/boot/dts/socfpga_arria5.dtsi | 11 ++++++++++ arch/arm/boot/dts/socfpga_cyclone5.dtsi | 11 ++++++++++ arch/arm/boot/dts/socfpga_vt.dts | 11 ++++++++++ 5 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt new file mode 100644 index 0000000..4897bea --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt @@ -0,0 +1,23 @@ +* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be + - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform + +Example: + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 129 4>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 3d62f47..967e27f 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -474,6 +474,17 @@ arm,data-latency = <2 1 1>; }; + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; @@ -528,7 +539,7 @@ }; sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x4000>; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index a85b404..6c87b70 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -27,6 +27,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + serial0@ffc02000 { clock-frequency = <100000000>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index a8716f6..ca41b0e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,6 +28,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index d1ec0ca..222313f 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -41,6 +41,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff700000 { phy-mode = "gmii"; status = "okay";