From patchwork Tue Jan 7 12:59:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 307634 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 221292C00E7 for ; Wed, 8 Jan 2014 00:01:15 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751387AbaAGNBL (ORCPT ); Tue, 7 Jan 2014 08:01:11 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:46663 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751343AbaAGNAj (ORCPT ); Tue, 7 Jan 2014 08:00:39 -0500 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MZ100EFL84WM580@mailout2.samsung.com>; Tue, 07 Jan 2014 22:00:33 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 5E.B6.09028.07AFBC25; Tue, 07 Jan 2014 22:00:32 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-1d-52cbfa70f9af Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 70.69.28157.07AFBC25; Tue, 07 Jan 2014 22:00:32 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MZ10091R83QNV20@mmp2.samsung.com>; Tue, 07 Jan 2014 22:00:32 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, thomas.ab@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH V2 07/10] clk/exynos5260: add macros and documentation for exynos5260 Date: Tue, 07 Jan 2014 18:29:05 +0530 Message-id: <1389099548-14649-8-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1389099548-14649-1-git-send-email-rahul.sharma@samsung.com> References: <1389099548-14649-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsWyRsSkRrfg1+kgg+8dlhbzj5xjtfi+6wu7 Re+Cq2wWmx5fY7WYcX4fk8XTCRfZLBa+iLeYsugwq0XHMkaLVbv+MDpweeycdZfd4861PWwe m5fUe/RtWcXo8XmTXABrFJdNSmpOZllqkb5dAlfG9C17WAte5VRs67zF0sC4KLKLkZNDQsBE 4sjXrawQtpjEhXvr2boYuTiEBJYySrTu2MgEU3T8agcbiC0kMJ1Rov23H4TdziTx+mAxiM0m oCsx++Azxi5GDg4RgUyJjVtyQcLMApsZJb5tVgOxhQXCJRpa1zKBlLAIqEqc/WkIEuYV8JDY 2t7FChKWEFCQmDPJBiTMKeApcXBGMzvEIg+Jp08uM4NcJiGwil3i0OnJYJexCAhIfJt8iAWi V1Zi0wFmiIMlJQ6uuMEygVF4ASPDKkbR1ILkguKk9CIjveLE3OLSvHS95PzcTYzAsD/971nf DsabB6wPMSYDjZvILCWanA+Mm7ySeENjMyMLUxNTYyNzSzPShJXEeRc9TAoSEkhPLEnNTk0t SC2KLyrNSS0+xMjEwSnVwLiwu+q72YYwH/477z1nuGVLs83haFY0Wu/7j/9j0h7181kzONn2 7vcwmGwivvOKZl3jgcCf+q6hc688X3NK/mOtr+Cp10kHJ4rGabHMinwX/0zd+5fRurtPLoQm VO5VvhFU+W2Kfaks6xp12WXZL3R1mRf4xZ3sPxX34uvDfBlzCZ/j34uWqimxFGckGmoxFxUn AgBri1jrkQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNIsWRmVeSWpSXmKPExsVy+t9jQd2CX6eDDCa80rWYf+Qcq8X3XV/Y LXoXXGWz2PT4GqvFjPP7mCyeTrjIZrHwRbzFlEWHWS06ljFarNr1h9GBy2PnrLvsHneu7WHz 2Lyk3qNvyypGj8+b5AJYoxoYbTJSE1NSixRS85LzUzLz0m2VvIPjneNNzQwMdQ0tLcyVFPIS c1NtlVx8AnTdMnOAblJSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZkzf soe14FVOxbbOWywNjIsiuxg5OSQETCSOX+1gg7DFJC7cWw9mCwlMZ5Ro/+0HYbczSbw+WAxi swnoSsw++Iyxi5GDQ0QgU2LjllyQMLPAZkaJb5vVQGxhgXCJhta1TCAlLAKqEmd/GoKEeQU8 JLa2d7GChCUEFCTmTLIBCXMKeEocnNHMDrHIQ+Lpk8vMExh5FzAyrGIUTS1ILihOSs810itO zC0uzUvXS87P3cQIjqpn0jsYVzVYHGIU4GBU4uF9sfdUkBBrYllxZe4hRgkOZiURXuYbp4OE eFMSK6tSi/Lji0pzUosPMSYD3TSRWUo0OR8Y8Xkl8YbGJuamxqaWJhYmZpakCSuJ8x5stQ4U EkhPLEnNTk0tSC2C2cLEwSnVwDgj6FLj8k4VPh+1e+xpFw4yck6rZGuY4ep2O1mxu4XV9djr 3ujdh75rKj183zcp7FHDza+Bu8M9q6vf/b9cUO+x8MC7c5XPHG4ZC7mfqJ+moxymObVw90Ol 3a2/gxcInlRSevzbYfOJIGa1j07xYbq3W53O/Y9W3M+65+YW1cjy3lZWp3tu8UosxRmJhlrM RcWJAN+sxt/uAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks. Signed-off-by: Rahul Sharma --- .../devicetree/bindings/clock/exynos5260-clock.txt | 299 ++++++++++++++++++++ include/dt-bindings/clk/exynos5260-clk.h | 234 +++++++++++++++ 2 files changed, 533 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 include/dt-bindings/clk/exynos5260-clk.h diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file mode 100644 index 0000000..ec180c0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt @@ -0,0 +1,299 @@ +* Samsung Exynos5260 Clock Controller + +The Exynos5260 clock controller encalsulate all CMUs which are +instantiaited independently from the device-tree. As a whole, +these CMUs generates and supplies clocks to various controllers +within the Exynos5260 SoC. + +Required Properties: + +- compatible: should be one of the following. + - First compatible should be one of the following + "exynos5260-cmu-top" + "exynos5260-cmu-peri" + "exynos5260-cmu-egl" + "exynos5260-cmu-kfc" + "exynos5260-cmu-g2d" + "exynos5260-cmu-mif" + "exynos5260-cmu-mfc" + "exynos5260-cmu-g3d" + "exynos5260-cmu-fsys" + "exynos5260-cmu-aud" + "exynos5260-cmu-isp" + "exynos5260-cmu-gscl" + "exynos5260-cmu-disp" + - Second compatible should be "samsung,exynos5260-clock". + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the each controller. Each +clock is assigned a MACRO constant. These constants are defined in +"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to specify +the clock which they consume. + +----------------------- + CMU_TOP clocks +----------------------- + + FIN_PLL + TOP_FOUT_DISP_PLL + TOP_FOUT_AUD_PLL + TOP_SCLK_MMC0 + TOP_SCLK_MMC1 + TOP_SCLK_MMC2 + TOP_SCLK_HDMIPHY + TOP_SCLK_FIMD1 + TOP_MOUT_FIMD1 + TOP_MOUT_DISP_PLL + +----------------------- + CMU_EGL clocks +----------------------- + + EGL_FOUT_EGL_PLL + EGL_FOUT_EGL_DPLL + +----------------------- + CMU_KFC clocks +----------------------- + + KFC_FOUT_KFC_PLL + +----------------------- + CMU_MIF clocks +----------------------- + + MIF_FOUT_MEM_PLL + MIF_FOUT_BUS_PLL + MIF_FOUT_MEDIA_PLL + +----------------------- + CMU_G3D clocks +----------------------- + + G3D_FOUT_G3D_PLL + G3D_CLK_G3D_HPM + G3D_CLK_G3D + +----------------------- + CMU_AUD clocks +----------------------- + + AUD_CLK_AUD_UART + AUD_CLK_PCM + AUD_CLK_I2S + AUD_CLK_DMAC + AUD_SCLK_AUD_UART + AUD_SCLK_PCM + AUD_SCLK_I2S + AUD_NR_CLK + +----------------------- + CMU_MFC clocks +----------------------- + + MFC_CLK_MFC + MFC_CLK_SMMU2_MFCM1 + MFC_CLK_SMMU2_MFCM0 + +----------------------- + CMU_GSCL clocks +----------------------- + + GSCL_CLK_PIXEL_GSCL1 + GSCL_CLK_PIXEL_GSCL0 + GSCL_CLK_MSCL1 + GSCL_CLK_MSCL0 + GSCL_CLK_GSCL1 + GSCL_CLK_GSCL0 + GSCL_CLK_FIMC_LITE_D + GSCL_CLK_FIMC_LITE_B + GSCL_CLK_FIMC_LITE_A + GSCL_CLK_CSIS1 + GSCL_CLK_CSIS0 + GSCL_CLK_SMMU3_LITE_D + GSCL_CLK_SMMU3_LITE_B + GSCL_CLK_SMMU3_LITE_A + GSCL_CLK_SMMU3_GSCL0 + GSCL_CLK_SMMU3_GSCL1 + GSCL_CLK_SMMU3_MSCL0 + GSCL_CLK_SMMU3_MSCL1 + GSCL_SCLK_CSIS1_WRAP + GSCL_SCLK_CSIS0_WRAP + +----------------------- + CMU_FSYS clocks +----------------------- + + FSYS_CLK_TSI + FSYS_CLK_USBLINK + FSYS_CLK_USBHOST20 + FSYS_CLK_USBDRD30 + FSYS_CLK_SROMC + FSYS_CLK_PDMA + FSYS_CLK_MMC2 + FSYS_CLK_MMC1 + FSYS_CLK_MMC0 + FSYS_CLK_RTIC + FSYS_CLK_SMMU_RTIC + FSYS_PHYCLK_USBDRD30 + FSYS_PHYCLK_USBHOST20 + FSYS_NR_CLK + +----------------------- + CMU_PERI clocks +----------------------- + + PERI_CLK_WDT_KFC + PERI_CLK_WDT_EGL + PERI_CLK_HSIC3 + PERI_CLK_HSIC2 + PERI_CLK_HSIC1 + PERI_CLK_HSIC0 + PERI_CLK_PCM + PERI_CLK_MCT + PERI_CLK_I2S + PERI_CLK_I2CHDMI + PERI_CLK_I2C7 + PERI_CLK_I2C6 + PERI_CLK_I2C5 + PERI_CLK_I2C4 + PERI_CLK_I2C9 + PERI_CLK_I2C8 + PERI_CLK_I2C11 + PERI_CLK_I2C10 + PERI_CLK_HDMICEC + PERI_CLK_EFUSE_WRITER + PERI_CLK_ABB + PERI_CLK_UART2 + PERI_CLK_UART1 + PERI_CLK_UART0 + PERI_CLK_ADC + PERI_CLK_TMU4 + PERI_CLK_TMU3 + PERI_CLK_TMU2 + PERI_CLK_TMU1 + PERI_CLK_TMU0 + PERI_CLK_SPI2 + PERI_CLK_SPI1 + PERI_CLK_SPI0 + PERI_CLK_SPDIF + PERI_CLK_PWM + PERI_CLK_UART4 + PERI_CLK_CHIPID + PERI_CLK_PROVKEY0 + PERI_CLK_PROVKEY1 + PERI_CLK_SECKEY + PERI_CLK_TOP_RTC + PERI_CLK_TZPC10 + PERI_CLK_TZPC9 + PERI_CLK_TZPC8 + PERI_CLK_TZPC7 + PERI_CLK_TZPC6 + PERI_CLK_TZPC5 + PERI_CLK_TZPC4 + PERI_CLK_TZPC3 + PERI_CLK_TZPC2 + PERI_CLK_TZPC1 + PERI_CLK_TZPC0 + PERI_SCLK_SPI2 + PERI_SCLK_SPI1 + PERI_SCLK_SPI0 + PERI_SCLK_SPDIF + PERI_SCLK_I2S + PERI_SCLK_PCM1 + PERI_SCLK_UART2 + PERI_SCLK_UART1 + PERI_SCLK_UART0 + +----------------------- + CMU_DISP clocks +----------------------- + + DISP_CLK_SMMU_TV + DISP_CLK_SMMU_FIMD1M1 + DISP_CLK_SMMU_FIMD1M0 + DISP_CLK_MIXER + DISP_CLK_MIPIPHY + DISP_CLK_HDMIPHY + DISP_CLK_HDMI + DISP_CLK_FIMD1 + DISP_CLK_DSIM1 + DISP_CLK_DPPHY + DISP_CLK_DP + DISP_SCLK_PIXEL + DISP_SCLK_HDMI + DISP_MOUT_HDMI_PHY_PIXEL + DISP_NR_CLK + +----------------------- + CMU_G2D clocks +----------------------- + + G2D_CLK_SMMU3_JPEG + G2D_CLK_MDMA + G2D_CLK_JPEG + G2D_CLK_G2D + G2D_CLK_SSS + G2D_CLK_SLIM_SSS + G2D_CLK_SMMU_SLIM_SSS + G2D_CLK_SMMU_SSS + G2D_CLK_SMMU_MDMA + G2D_CLK_SMMU3_G2D + +----------------------- + CMU_ISP clocks +----------------------- + + ISP_CLK_GIC + ISP_CLK_WDT + ISP_CLK_UART + ISP_CLK_SPI1 + ISP_CLK_SPI0 + ISP_CLK_SMMU_SCALERP + ISP_CLK_SMMU_SCALERC + ISP_CLK_SMMU_ISPCX + ISP_CLK_SMMU_ISP + ISP_CLK_SMMU_FD + ISP_CLK_SMMU_DRC + ISP_CLK_PWM + ISP_CLK_MTCADC + ISP_CLK_MPWM + ISP_CLK_MCUCTL + ISP_CLK_I2C1 + ISP_CLK_I2C0 + ISP_CLK_FIMC_SCALERP + ISP_CLK_FIMC_SCALERC + ISP_CLK_FIMC + ISP_CLK_FIMC_FD + ISP_CLK_FIMC_DRC + ISP_CLK_CA5 + ISP_SCLK_SPI0_EXT + ISP_SCLK_SPI1_EXT + ISP_SCLK_UART_EXT + + +Example 1: An example of a clock controller node is listed below. + + cmu_disp: clock-controller@0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the + peri clock controller. Refer to the standard clock bindings for + information about 'clocks' and 'clock-names' property. + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + diff --git a/include/dt-bindings/clk/exynos5260-clk.h b/include/dt-bindings/clk/exynos5260-clk.h new file mode 100644 index 0000000..d2fb7fa --- /dev/null +++ b/include/dt-bindings/clk/exynos5260-clk.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Provides Constants for Exynos5260 clocks. +*/ + +#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H +#define _DT_BINDINGS_CLK_EXYNOS5260_H + +#define ID_NONE 0 + +/* + * Clock names: XXXXXX_YYYYY_ZZZZZ + * |------| |----| |----| + * cmu type IP +*/ + +/* list of clocks for CMU_TOP */ +#define FIN_PLL 1 +#define TOP_FOUT_DISP_PLL 2 +#define TOP_FOUT_AUD_PLL 3 +#define TOP_SCLK_MMC0 4 +#define TOP_SCLK_MMC1 5 +#define TOP_SCLK_MMC2 6 +#define TOP_SCLK_HDMIPHY 7 +#define TOP_SCLK_FIMD1 8 +#define TOP_MOUT_FIMD1 9 +#define TOP_MOUT_DISP_PLL 10 +#define TOP_NR_CLK 11 + +/* list of clocks for CMU_EGL */ +#define EGL_FOUT_EGL_PLL 1 +#define EGL_FOUT_EGL_DPLL 2 +#define EGL_NR_CLK 3 + +/* list of clocks for CMU_KFC */ +#define KFC_FOUT_KFC_PLL 1 +#define KFC_NR_CLK 2 + +/* list of clocks for CMU_MIF */ +#define MIF_FOUT_MEM_PLL 1 +#define MIF_FOUT_BUS_PLL 2 +#define MIF_FOUT_MEDIA_PLL 3 +#define MIF_NR_CLK 4 + +/* list of clocks for CMU_G3D */ +#define G3D_FOUT_G3D_PLL 1 +#define G3D_CLK_G3D_HPM 2 +#define G3D_CLK_G3D 3 +#define G3D_NR_CLK 4 + +/* list of clocks for CMU_AUD */ +#define AUD_CLK_AUD_UART 1 +#define AUD_CLK_PCM 2 +#define AUD_CLK_I2S 3 +#define AUD_CLK_DMAC 4 +#define AUD_SCLK_AUD_UART 5 +#define AUD_SCLK_PCM 6 +#define AUD_SCLK_I2S 7 +#define AUD_NR_CLK 8 + +/* list of clocks for CMU_MFC */ +#define MFC_CLK_MFC 1 +#define MFC_CLK_SMMU2_MFCM1 2 +#define MFC_CLK_SMMU2_MFCM0 3 +#define MFC_NR_CLK 4 + +/* list of clocks for CMU_GSCL */ +#define GSCL_CLK_PIXEL_GSCL1 1 +#define GSCL_CLK_PIXEL_GSCL0 2 +#define GSCL_CLK_MSCL1 3 +#define GSCL_CLK_MSCL0 4 +#define GSCL_CLK_GSCL1 5 +#define GSCL_CLK_GSCL0 6 +#define GSCL_CLK_FIMC_LITE_D 7 +#define GSCL_CLK_FIMC_LITE_B 8 +#define GSCL_CLK_FIMC_LITE_A 9 +#define GSCL_CLK_CSIS1 10 +#define GSCL_CLK_CSIS0 11 +#define GSCL_CLK_SMMU3_LITE_D 12 +#define GSCL_CLK_SMMU3_LITE_B 13 +#define GSCL_CLK_SMMU3_LITE_A 14 +#define GSCL_CLK_SMMU3_GSCL0 15 +#define GSCL_CLK_SMMU3_GSCL1 16 +#define GSCL_CLK_SMMU3_MSCL0 17 +#define GSCL_CLK_SMMU3_MSCL1 18 +#define GSCL_SCLK_CSIS1_WRAP 19 +#define GSCL_SCLK_CSIS0_WRAP 20 +#define GSCL_NR_CLK 21 + +/* list of clocks for CMU_FSYS */ +#define FSYS_CLK_TSI 1 +#define FSYS_CLK_USBLINK 2 +#define FSYS_CLK_USBHOST20 3 +#define FSYS_CLK_USBDRD30 4 +#define FSYS_CLK_SROMC 5 +#define FSYS_CLK_PDMA 6 +#define FSYS_CLK_MMC2 7 +#define FSYS_CLK_MMC1 8 +#define FSYS_CLK_MMC0 9 +#define FSYS_CLK_RTIC 10 +#define FSYS_CLK_SMMU_RTIC 11 +#define FSYS_PHYCLK_USBDRD30 12 +#define FSYS_PHYCLK_USBHOST20 13 +#define FSYS_NR_CLK 14 + +/* list of clocks for CMU_PERI */ +#define PERI_CLK_WDT_KFC 1 +#define PERI_CLK_WDT_EGL 2 +#define PERI_CLK_HSIC3 3 +#define PERI_CLK_HSIC2 4 +#define PERI_CLK_HSIC1 5 +#define PERI_CLK_HSIC0 6 +#define PERI_CLK_PCM 7 +#define PERI_CLK_MCT 8 +#define PERI_CLK_I2S 9 +#define PERI_CLK_I2CHDMI 10 +#define PERI_CLK_I2C7 11 +#define PERI_CLK_I2C6 12 +#define PERI_CLK_I2C5 13 +#define PERI_CLK_I2C4 14 +#define PERI_CLK_I2C9 15 +#define PERI_CLK_I2C8 16 +#define PERI_CLK_I2C11 17 +#define PERI_CLK_I2C10 18 +#define PERI_CLK_HDMICEC 19 +#define PERI_CLK_EFUSE_WRITER 20 +#define PERI_CLK_ABB 21 +#define PERI_CLK_UART2 22 +#define PERI_CLK_UART1 23 +#define PERI_CLK_UART0 24 +#define PERI_CLK_ADC 25 +#define PERI_CLK_TMU4 26 +#define PERI_CLK_TMU3 27 +#define PERI_CLK_TMU2 28 +#define PERI_CLK_TMU1 29 +#define PERI_CLK_TMU0 30 +#define PERI_CLK_SPI2 31 +#define PERI_CLK_SPI1 32 +#define PERI_CLK_SPI0 33 +#define PERI_CLK_SPDIF 34 +#define PERI_CLK_PWM 35 +#define PERI_CLK_UART4 36 +#define PERI_CLK_CHIPID 37 +#define PERI_CLK_PROVKEY0 38 +#define PERI_CLK_PROVKEY1 39 +#define PERI_CLK_SECKEY 40 +#define PERI_CLK_TOP_RTC 41 +#define PERI_CLK_TZPC10 42 +#define PERI_CLK_TZPC9 43 +#define PERI_CLK_TZPC8 44 +#define PERI_CLK_TZPC7 45 +#define PERI_CLK_TZPC6 46 +#define PERI_CLK_TZPC5 47 +#define PERI_CLK_TZPC4 48 +#define PERI_CLK_TZPC3 49 +#define PERI_CLK_TZPC2 50 +#define PERI_CLK_TZPC1 51 +#define PERI_CLK_TZPC0 52 +#define PERI_SCLK_SPI2 53 +#define PERI_SCLK_SPI1 54 +#define PERI_SCLK_SPI0 55 +#define PERI_SCLK_SPDIF 56 +#define PERI_SCLK_I2S 57 +#define PERI_SCLK_PCM1 58 +#define PERI_SCLK_UART2 59 +#define PERI_SCLK_UART1 60 +#define PERI_SCLK_UART0 61 +#define PERI_NR_CLK 62 + +/* list of clocks for CMU_DISP */ +#define DISP_CLK_SMMU_TV 1 +#define DISP_CLK_SMMU_FIMD1M1 2 +#define DISP_CLK_SMMU_FIMD1M0 3 +#define DISP_CLK_MIXER 4 +#define DISP_CLK_MIPIPHY 5 +#define DISP_CLK_HDMIPHY 6 +#define DISP_CLK_HDMI 7 +#define DISP_CLK_FIMD1 8 +#define DISP_CLK_DSIM1 9 +#define DISP_CLK_DPPHY 10 +#define DISP_CLK_DP 11 +#define DISP_SCLK_PIXEL 12 +#define DISP_SCLK_HDMI 13 +#define DISP_MOUT_HDMI_PHY_PIXEL 14 +#define DISP_NR_CLK 15 + +/* list of clocks for CMU_G2D */ +#define G2D_CLK_SMMU3_JPEG 1 +#define G2D_CLK_MDMA 2 +#define G2D_CLK_JPEG 3 +#define G2D_CLK_G2D 4 +#define G2D_CLK_SSS 5 +#define G2D_CLK_SLIM_SSS 6 +#define G2D_CLK_SMMU_SLIM_SSS 7 +#define G2D_CLK_SMMU_SSS 8 +#define G2D_CLK_SMMU_MDMA 9 +#define G2D_CLK_SMMU3_G2D 10 +#define G2D_NR_CLK 11 + +/* list of clocks for CMU_ISP */ +#define ISP_CLK_GIC 1 +#define ISP_CLK_WDT 2 +#define ISP_CLK_UART 3 +#define ISP_CLK_SPI1 4 +#define ISP_CLK_SPI0 5 +#define ISP_CLK_SMMU_SCALERP 6 +#define ISP_CLK_SMMU_SCALERC 7 +#define ISP_CLK_SMMU_ISPCX 8 +#define ISP_CLK_SMMU_ISP 9 +#define ISP_CLK_SMMU_FD 10 +#define ISP_CLK_SMMU_DRC 11 +#define ISP_CLK_PWM 12 +#define ISP_CLK_MTCADC 13 +#define ISP_CLK_MPWM 14 +#define ISP_CLK_MCUCTL 15 +#define ISP_CLK_I2C1 16 +#define ISP_CLK_I2C0 17 +#define ISP_CLK_FIMC_SCALERP 18 +#define ISP_CLK_FIMC_SCALERC 19 +#define ISP_CLK_FIMC 20 +#define ISP_CLK_FIMC_FD 21 +#define ISP_CLK_FIMC_DRC 22 +#define ISP_CLK_CA5 23 +#define ISP_SCLK_SPI0_EXT 24 +#define ISP_SCLK_SPI1_EXT 25 +#define ISP_SCLK_UART_EXT 26 +#define ISP_NR_CLK 27 + +#endif