From patchwork Wed Dec 4 22:52:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dinguyen@altera.com X-Patchwork-Id: 296652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4A76F2C008E for ; Thu, 5 Dec 2013 09:54:58 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756141Ab3LDWy5 (ORCPT ); Wed, 4 Dec 2013 17:54:57 -0500 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:19680 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756142Ab3LDWyy (ORCPT ); Wed, 4 Dec 2013 17:54:54 -0500 Received: from mail171-tx2-R.bigfish.com (10.9.14.245) by TX2EHSOBE012.bigfish.com (10.9.40.32) with Microsoft SMTP Server id 14.1.225.22; Wed, 4 Dec 2013 22:54:54 +0000 Received: from mail171-tx2 (localhost [127.0.0.1]) by mail171-tx2-R.bigfish.com (Postfix) with ESMTP id 4B4B4240310; Wed, 4 Dec 2013 22:54:54 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail171-tx2: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail171-tx2 (localhost.localdomain [127.0.0.1]) by mail171-tx2 (MessageSwitch) id 1386197692619485_15044; Wed, 4 Dec 2013 22:54:52 +0000 (UTC) Received: from TX2EHSMHS009.bigfish.com (unknown [10.9.14.232]) by mail171-tx2.bigfish.com (Postfix) with ESMTP id 6EE9CE0049; Wed, 4 Dec 2013 22:54:52 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by TX2EHSMHS009.bigfish.com (10.9.99.109) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 4 Dec 2013 22:54:51 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Wed, 4 Dec 2013 14:42:58 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rB4Msjnc002799; Wed, 4 Dec 2013 14:54:49 -0800 (PST) From: To: , , , , , , , , , CC: , , , Dinh Nguyen Subject: [PATCHv3 2/4] arm: dts: Add a system manager compatible property Date: Wed, 4 Dec 2013 16:52:54 -0600 Message-ID: <1386197576-3825-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386197576-3825-1-git-send-email-dinguyen@altera.com> References: <1386197576-3825-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dinh Nguyen The "altr,sysmgr-sdmmc-sdr" compatible property is used for the SOCFPGA clk-sysmgr driver. This property represents the register inside the system manager that controls the clock phase of the SD/MMC driver. Signed-off-by: Dinh Nguyen --- v3: Cannot use the syscon driver along with the clock because as of v3.13-rc1, the syscon driver is loaded after the clocks. v2: Add syscon --- .../bindings/arm/altera/socfpga-system.txt | 10 ++++++++++ arch/arm/boot/dts/socfpga.dtsi | 14 +++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt index f4d04a0..7a6c7ed 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt @@ -5,9 +5,19 @@ Required properties: - reg : Should contain 1 register ranges(address and length) - cpu1-start-addr : CPU1 start address in hex. +Optional properties: +- compatible = "altr,sysmgr-sdmmc-sdr". This compatible property is used +to represent the clock phase settings for the SD/MMC IP. + Example: sysmgr@ffd08000 { compatible = "altr,sys-mgr"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; + + sysmgr_sdr_mmc: sysmgr_sdr_mmc { + #clock-cells = <0>; + compatible = "altr,sysmgr-sdmmc-sdr"; + reg = <0x108 1>; + }; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..a6a13b3 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -522,9 +522,17 @@ reg = <0xffd05000 0x1000>; }; - sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x4000>; + sysmgr: sysmgr@ffd08000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,sys-mgr"; + reg = <0xffd08000 0x4000>; + + sysmgr_sdr_mmc: sysmgr_sdr_mmc { + #clock-cells = <0>; + compatible = "altr,sysmgr-sdmmc-sdr"; + reg = <0x108 1>; }; + }; }; };