From patchwork Thu Nov 7 06:42:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 289204 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 322462C007A for ; Thu, 7 Nov 2013 17:44:47 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757298Ab3KGGon (ORCPT ); Thu, 7 Nov 2013 01:44:43 -0500 Received: from mail-pd0-f179.google.com ([209.85.192.179]:60148 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751636Ab3KGGom (ORCPT ); Thu, 7 Nov 2013 01:44:42 -0500 Received: by mail-pd0-f179.google.com with SMTP id y10so149197pdj.38 for ; Wed, 06 Nov 2013 22:44:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HBD6Yzlm/hPfUWiIJonpeNYoGq7L/zb9Cx5UcpazZsk=; b=XivDsA7RS+WQ9vN9ZB751h30RAyKUGpMSmnHxDxn6IEV4gITz72njYG+bxQMUZaNLg H9gVm/nPTzKPRzsfjIxZF/txMip82mU4b/pUp7nc6PxjnspGTHsIps5Ui60V3KKOGfcv GDLQLHHX05VxAR9VIkaCfeVlvSACgerqQRiQ+8ImTHUs0X+GBrKT33/zDashK4PuyHDZ wAKdIr+ykNukr3NMzP7OclpUc15pyRyBv+3a2pJCZxZRtLivb6N9VCJqB/cAJQju5m4h sfxSOo3uLr4xwDI4qpv8pTyy8mByKG4dY1oRGnpJMebYezawP+HdyOWos/XQHed1JqKE SnGA== X-Gm-Message-State: ALoCoQkPyflKTqSiZJfhMCgrXDuQpP9pdUfrzUkU+Tu+TwL358D9XJS7XQOrOLmz2RjF5HQNr9Fy X-Received: by 10.68.133.133 with SMTP id pc5mr7247759pbb.131.1383806681462; Wed, 06 Nov 2013 22:44:41 -0800 (PST) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id nj9sm2637552pbc.13.2013.11.06.22.44.38 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 06 Nov 2013 22:44:40 -0800 (PST) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: devicetree@vger.kernel.org, kgene.kim@samsung.com, sachin.kamat@linaro.org, Prathyush K Subject: [PATCH 1/1] ARM: EXYNOS: Add enable property to power domains Date: Thu, 7 Nov 2013 12:12:55 +0530 Message-Id: <1383806575-28401-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Prathyush K Different power domains of Exynos SOCs have different enable values. E.g. Exynos5250: ROTATOR_MEM_CONFIGURATION -> 0x3 GSCL_CONFIGURATION -> 0x7 Currently, there is no way to differentiate between these power domains and we write default value of 0x7 to turn on all the power domains. This patch adds a new 'enable' property to the power domain structure. This enable value can be set from the device tree by adding a property 'enable' in the device node. If no such property is found, the default value of 0x7 is used as enable value. Signed-off-by: Prathyush K Signed-off-by: Sachin Kamat --- .../bindings/arm/exynos/power_domain.txt | 5 +++++ arch/arm/mach-exynos/pm_domains.c | 10 +++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 5216b419016a..6b24b234617c 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -9,6 +9,10 @@ Required Properties: - reg: physical base address of the controller and length of memory mapped region. +Optional Properties: +- enable: enable value of the register which is used to turn on the power + domain. If no enable is specificed, default value of 0x7 is used. + Node of a device using power domains must have a samsung,power-domain property defined with a phandle to respective power domain. @@ -17,6 +21,7 @@ Example: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x10>; + enable = <0x1>; }; Example of the node using power domain: diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 1703593e366c..84e0483a0500 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -33,6 +33,7 @@ struct exynos_pm_domain { char const *name; bool is_off; struct generic_pm_domain pd; + u32 enable; }; static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) @@ -45,13 +46,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base; - pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0; + pwr = power_on ? pd->enable : 0; __raw_writel(pwr, base); /* Wait max 1ms */ timeout = 10; - while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) { + while ((__raw_readl(base + 0x4) & pd->enable) != pwr) { if (!timeout) { op = (power_on) ? "enable" : "disable"; pr_err("Power domain %s %s failed\n", domain->name, op); @@ -164,6 +165,9 @@ static __init int exynos4_pm_init_power_domain(void) return -ENOMEM; } + if (of_property_read_u32(np, "enable", &pd->enable)) + pd->enable = S5P_INT_LOCAL_PWR_EN; + pd->pd.name = kstrdup(np->name, GFP_KERNEL); pd->name = pd->pd.name; pd->base = of_iomap(np, 0); @@ -173,7 +177,7 @@ static __init int exynos4_pm_init_power_domain(void) platform_set_drvdata(pdev, pd); - on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; + on = __raw_readl(pd->base + 0x4) & pd->enable; pm_genpd_init(&pd->pd, NULL, !on); }