From patchwork Thu Dec 1 17:04:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Clayton X-Patchwork-Id: 701603 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tV3bH2M6Xz9sCZ for ; Fri, 2 Dec 2016 04:06:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PAc4pq1n"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755290AbcLARGE (ORCPT ); Thu, 1 Dec 2016 12:06:04 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:35048 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760614AbcLARFH (ORCPT ); Thu, 1 Dec 2016 12:05:07 -0500 Received: by mail-pg0-f67.google.com with SMTP id p66so5150395pga.2; Thu, 01 Dec 2016 09:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=Xx6wNUjlNwSmMhzChP40cnOmxUPBq6phUglZDxdxlLI=; b=PAc4pq1ncixXBAvCVpToWvOrfjybHU4WGBTd4vFhztVSfhgNHuxwxvXO04PaoAnd2t hiHnmuD/kwvmxk2ZoGuMXQFHRKybSuaNSfvsoF5edLnLK4FMsPyrzUehxL40FRKAIMNX on+1tcLfd2gszPB6+f7vVupvEiG+EK2nuccKMk7D1Mo3zbR+1ToNuaSrDHWPO6ZzwiPO FdiTrBSXs9FAroc/Kz5Swn/UvorGI000J8e3UYcTH91MarkUzEc6ZVo5f0nRtNo4kzAh Ut5Tek+Kq5yPt2JLNdiZh7sR6Rm/hJitCE2+jzuJqpaRwBqcIhzEVVHLSU/lfQ6/gKIH Tlmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Xx6wNUjlNwSmMhzChP40cnOmxUPBq6phUglZDxdxlLI=; b=hmSshdnuHmFAoi8TJaNhSDB+PA/QMPxFfDuOvsSGa0w5MeXdFg1So1L6uOWGyXnzTY LAPGuKlOiNnCstdkvhfgz8uA78HlGr3WFxpo4DZgsrJv2hFXb9YnFVUEucL2QVlg6vSc yNOc2TSh+ALVAxuE2ygSjTRgAhiugvp0fPf7XjuQucQUdxzhC1BlyYlvJDXVciJ7CKV1 M18Slt9bqLl5UKyrgb/FEgNES93fwY+L+0fPbIGde2XBleZjLB2KT4dkQ6UuNX4AtWcw J0akPNmpO72JGkiL9Pxog8AnVknJzigUcUbI7Eimeskk2SXju8NTj3iL9Nki037SczV0 lQFA== X-Gm-Message-State: AKaTC001NzmZxjdC8W2/pgc/u5NOD8LCQnY5Mh6MfxPGPgNAndwRFQdaMpVTcv89wVGMpA== X-Received: by 10.99.229.17 with SMTP id r17mr71070561pgh.149.1480611906366; Thu, 01 Dec 2016 09:05:06 -0800 (PST) Received: from jclayton-pc.columbia.uniwest.com (68-185-59-186.static.knwc.wa.charter.com. [68.185.59.186]) by smtp.gmail.com with ESMTPSA id 13sm1563530pfz.30.2016.12.01.09.05.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Dec 2016 09:05:05 -0800 (PST) From: Joshua Clayton To: Alan Tull , Moritz Fischer , Rob Herring , Mark Rutland , Russell King Cc: Joshua Clayton , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] doc: dt: add cyclone-spi binding document Date: Thu, 1 Dec 2016 09:04:51 -0800 Message-Id: <137f03de76e5f865430b17ca247e8f73e3315c8d.1480551148.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe a cyclonei-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Moritz Fischer Acked-by: Rob Herring --- .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt diff --git a/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt new file mode 100644 index 0000000..3f515c7 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt @@ -0,0 +1,25 @@ +Altera Cyclone Passive Serial SPI FPGA Manager + +Altera Cyclone FPGAs support a method of loading the bitstream over what is +referred to as "passive serial". +The passive serial link is not technically spi, and might require extra +circuits in order to play nicely with other spi slaves on the same bus. + +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf + +Required properties: +- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr" +- reg : spi slave id of the fpga +- config-gpios : config pin (referred to as nCONFIG in the cyclone manual) +- status-gpios : status pin (referred to as nSTATUS in the cyclone manual) + +both gpio pins are normally active low open drain. + +Example: + fpga_spi: evi-fpga-spi@0 { + compatible = "altr,cyclone-ps-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + config-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + status-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + };