| Message ID | cover.1691496290.git.quic_schowdhu@quicinc.com |
|---|---|
| Headers | show |
| Series | misc: Add driver support for Data Capture and Compare unit(DCC) | expand |
On Tue, Aug 08, 2023 at 05:58:26PM +0530, Souradeep Chowdhury wrote: > diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc > index 27ed5919d21b..7f588580a906 100644 > --- a/Documentation/ABI/testing/debugfs-driver-dcc > +++ b/Documentation/ABI/testing/debugfs-driver-dcc > @@ -1,4 +1,4 @@ > -What: /sys/kernel/debug/dcc/.../ready > +What: /sys/kernel/debug/qcom-dcc/.../ready > Date: December 2022 Looks like this patch set is getting closer to being accepted, please keep the date updated accordingly. > +#define DCC_LL_NUM_INFO 0x10 > +#define DCC_LL_LOCK 0x00 > +#define DCC_LL_CFG 0x04 > +#define DCC_LL_BASE 0x08 > +#define DCC_FD_BASE 0x0c > +#define DCC_LL_OFFSET 0x80 > +#define DCC_LL_TIMEOUT 0x10 > +#define DCC_LL_INT_ENABLE 0x18 > +#define DCC_LL_INT_STATUS 0x1c > +#define DCC_LL_SW_TRIGGER 0x2c > +#define DCC_LL_BUS_ACCESS_STATUS 0x30 > + > +/* Default value used if a bit 6 in the HW_INFO register is set. */ > +#define DCC_FIX_LOOP_OFFSET 16 > + > +/* Mask to find version info from HW_Info register */ > +#define DCC_VER_INFO_MASK BIT(9) > + > +#define MAX_DCC_OFFSET GENMASK(9, 2) > +#define MAX_DCC_LEN GENMASK(6, 0) > +#define MAX_LOOP_CNT GENMASK(7, 0) > +#define MAX_LOOP_ADDR 10 > + > +#define DCC_ADDR_DESCRIPTOR 0x00 > +#define DCC_ADDR_LIMIT 27 > +#define DCC_WORD_SIZE sizeof(u32) > +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) > +#define DCC_LOOP_DESCRIPTOR BIT(30) > +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) > +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) > +#define DCC_STATUS_MASK GENMASK(1, 0) > +#define DCC_LOCK_MASK BIT(0) > +#define DCC_LOOP_OFFSET_MASK BIT(6) > +#define DCC_TRIGGER_MASK BIT(9) > + > +#define DCC_WRITE_MASK BIT(15) > +#define DCC_WRITE_OFF_MASK GENMASK(7, 0) > +#define DCC_WRITE_LEN_MASK GENMASK(14, 8) > + > +#define DCC_READ_IND 0x00 > +#define DCC_WRITE_IND (BIT(28)) > + > +#define DCC_AHB_IND 0x00 > +#define DCC_APB_IND BIT(29) > + > +#define DCC_MAX_LINK_LIST 8 > + > +#define DCC_VER_MASK2 GENMASK(5, 0) > + > +#define DCC_SRAM_WORD_LENGTH 4 > + > +#define DCC_RD_MOD_WR_ADDR 0xC105E > + > +enum dcc_descriptor_type { > + DCC_READ_TYPE, > + DCC_LOOP_TYPE, > + DCC_READ_WRITE_TYPE, > + DCC_WRITE_TYPE > +}; Can you fix the spacing in the macros? > +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) u32 loop_cnt Lucas
DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes. In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes. The DCC driver provides the user with debugfs interface to configure the register addresses. The options that the DCC hardware provides include reading from registers, writing to registers, first reading and then writing to registers and looping through the values of the same register. In certain cases a register write needs to be executed for accessing the rest of the registers, also the user might want to record the changing values of a register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by debugfs files once the driver is probed. The details and usage of this debugfs files are documented in Documentation/ABI/testing/debugfs-driver-dcc. As an example let us consider a couple of debug scenarios where DCC has been proved to be effective for debugging purposes:- i)TimeStamp Related Issue On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper timestamp values. Proper timestamp: Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e Zero timestamp: Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 Now this is a non-fatal issue and doesn't need a system reset, but still needs to be rootcaused and fixed for those who do care about coresight etm traces. Since this is a timestamp issue, we would be looking for any timestamp related clocks and such. We get all the clk register details from IP documentation and configure it via DCC config_read debugfs node. Before that we set the current linked list. /* Program the linked list with the addresses */ echo R 0x10c004 > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c008 > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c00c > /sys/kernel/debug/qcom-dcc/../3/config echo R 0x10c010 > /sys/kernel/debug/qcom-dcc/../3/config ..... and so on for other timestamp related clk registers /* Other way of specifying is in "addr len" pair, in below case it specifies to capture 4 words starting 0x10C004 */ echo R 0x10C004 4 > /sys/kernel/debug/qcom-dcc/../3/config_read /* Enable DCC */ echo 1 > /sys/kernel/debug/qcom-dcc/../3/enable /* Run the timestamp test for working case */ /* Send SW trigger */ echo 1 > /sys/kernel/debug/qcom-dcc/../trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram1.bin /* Run the timestamp test for non-working case */ /* Send SW trigger */ echo 1 > /sys/kernel/debug/qcom-dcc/../trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram2.bin Get the parser from [1] and checkout the latest branch. /* Parse the SRAM bin */ python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python dcc_parser.py -s dcc_sram2.bin --v2 -o output/ Sample parsed output of dcc_sram1.bin: <hwioDump version="1"> <timestamp>03/14/21</timestamp> <generator>Linux DCC Parser</generator> <chip name="None" version="None"> <register address="0x0010c004" value="0x80000000" /> <register address="0x0010c008" value="0x00000008" /> <register address="0x0010c00c" value="0x80004220" /> <register address="0x0010c010" value="0x80000000" /> </chip> <next_ll_offset>next_ll_offset : 0x1c </next_ll_offset> </hwioDump> ii)NOC register errors A particular class of registers called NOC which are functional registers was reporting errors while logging the values.To trace these errors the DCC has been used effectively. The steps followed were similar to the ones mentioned above. In addition to NOC registers a few other dependent registers were configured in DCC to monitor it's values during a crash. A look at the dependent register values revealed that the crash was happening due to a secured access to one of these dependent registers. All these debugging activity and finding the root cause was achieved using DCC. DCC parser is available at the following open source location https://git.codelinaro.org/clo/le/platform/vendor/qcom-opensource/tools/-/tree/opensource-tools.lnx.1.0.r176-rel/dcc_parser Changes in v26 * Fixed the build error in V25 of the patch series Changes in v25 * Updated the documentation of the structure dcc_config_entry as per the comments in V23 * Updated the documentation of the dcc Kconfig definition as per comment in V24 * Used u64 where applicable * Removed the mutex locks where it is not needed * Removed the use of unlikely keyword Souradeep Chowdhury (3): dt-bindings: misc: qcom,dcc: Add the dtschema misc: dcc: Add driver support for Data Capture and Compare unit(DCC) MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support Documentation/ABI/testing/debugfs-driver-dcc | 10 +- .../devicetree/bindings/misc/qcom,dcc.yaml | 44 + MAINTAINERS | 8 + drivers/misc/Kconfig | 8 + drivers/misc/Makefile | 1 + drivers/misc/qcom-dcc.c | 1310 +++++++++++++++++ 6 files changed, 1376 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/qcom,dcc.yaml create mode 100644 drivers/misc/qcom-dcc.c -- 2.17.1