| Message ID | cover.1686217906.git.quic_varada@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable IPQ9754 USB | expand |
On 08/06/2023 13:03, Varadarajan Narayanan wrote: > Add USB phy and controller related nodes > > SS PHY need two supplies and HS PHY needs three supplies. 0.925V > and 3.3V are from fixed regulators and 1.8V is generated from > PMIC's LDO > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > Changes in v13: > - Move fixed regulator definitions from SoC dtsi to board dts > - Remove 'dr_mode' from SoC dtsi > - Move 'status' property to the end > Changes in v12: > - Rebase > Changes in v11: > - Rename dwc_0 -> usb_0_dwc3 > Changes in v10: > - Fix regulator definitions > Changes in v8: > - Change clocks order to match the bindings > Changes in v7: > - Change com_aux -> cfg_ahb > Changes in v6: > - Introduce fixed regulators for the phy > - Resolved all 'make dtbs_check' messages > > Changes in v5: > - Fix additional comments > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml > - 'make dtbs_check' giving the following messages since > ipq9574 doesn't have power domains. Hope this is ok > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > Changes in v4: > - Use newer bindings without subnodes > - Fix coding style issues > > Changes in v3: > - Insert the nodes at proper location > > Changes in v2: > - Fixed issues flagged by Krzysztof > - Fix issues reported by make dtbs_check > - Remove NOC related clocks (to be added with proper > interconnect support) > --- > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 18 ++++++ > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 +++++++++++++++++++++++++++++ > 2 files changed, 103 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > index 2b3ed8d..8261a2b 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > @@ -21,6 +21,24 @@ > chosen { > stdout-path = "serial0:115200n8"; > }; > + > + regulator_fixed_3p3: s3300 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-name = "fixed_3p3"; > + }; > + > + regulator_fixed_0p925: s0925 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <925000>; > + regulator-max-microvolt = <925000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-name = "fixed_0p925"; > + }; > }; Let me repeat from v13, so that it is not lost (please excuse me for the spam): Nit: these two regulators are not references from SoC dtsi. So they don't have to be a part of this commit and can be moved to one of the next commits (I'd prefer the last one). > > &blsp1_uart2 { > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 0baeb10..feabc19 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -465,6 +465,91 @@ > status = "disabled"; > }; > > + usb_0_qusbphy: phy@7b000 { > + compatible = "qcom,ipq9574-qusb2-phy"; > + reg = <0x0007b000 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&xo_board_clk>; > + clock-names = "cfg_ahb", > + "ref"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + status = "disabled"; > + }; > + > + usb_0_qmpphy: phy@7d000 { > + compatible = "qcom,ipq9574-qmp-usb3-phy"; > + reg = <0x0007d000 0xa00>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_AUX_CLK>, > + <&xo_board_clk>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_USB0_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "cfg_ahb", > + "pipe"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>, > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > + reset-names = "phy", > + "phy_phy"; > + > + #clock-cells = <0>; > + clock-output-names = "usb0_pipe_clk"; > + > + status = "disabled"; > + }; > + > + usb3: usb@8af8800 { > + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; > + reg = <0x08af8800 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_SNOC_USB_CLK>, > + <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_ANOC_USB_AXI_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi"; > + > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + assigned-clock-rates = <200000000>, > + <24000000>; > + > + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pwr_event"; > + > + resets = <&gcc GCC_USB_BCR>; > + status = "disabled"; > + > + usb_0_dwc3: usb@8a00000 { > + compatible = "snps,dwc3"; > + reg = <0x8a00000 0xcd00>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > intc: interrupt-controller@b000000 { > compatible = "qcom,msm-qgic2"; > reg = <0x0b000000 0x1000>, /* GICD */
On Thu, Jun 08, 2023 at 02:06:49PM +0300, Dmitry Baryshkov wrote: > On 08/06/2023 13:03, Varadarajan Narayanan wrote: > >Add USB phy and controller related nodes > > > >SS PHY need two supplies and HS PHY needs three supplies. 0.925V > >and 3.3V are from fixed regulators and 1.8V is generated from > >PMIC's LDO > > > >Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > >--- > > Changes in v13: > > - Move fixed regulator definitions from SoC dtsi to board dts > > - Remove 'dr_mode' from SoC dtsi > > - Move 'status' property to the end > > Changes in v12: > > - Rebase > > Changes in v11: > > - Rename dwc_0 -> usb_0_dwc3 > > Changes in v10: > > - Fix regulator definitions > > Changes in v8: > > - Change clocks order to match the bindings > > Changes in v7: > > - Change com_aux -> cfg_ahb > > Changes in v6: > > - Introduce fixed regulators for the phy > > - Resolved all 'make dtbs_check' messages > > > > Changes in v5: > > - Fix additional comments > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > - 'make dtbs_check' giving the following messages since > > ipq9574 doesn't have power domains. Hope this is ok > > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > > > Changes in v4: > > - Use newer bindings without subnodes > > - Fix coding style issues > > > > Changes in v3: > > - Insert the nodes at proper location > > > > Changes in v2: > > - Fixed issues flagged by Krzysztof > > - Fix issues reported by make dtbs_check > > - Remove NOC related clocks (to be added with proper > > interconnect support) > >--- > > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 18 ++++++ > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 +++++++++++++++++++++++++++++ > > 2 files changed, 103 insertions(+) > > > >diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > >index 2b3ed8d..8261a2b 100644 > >--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > >+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > >@@ -21,6 +21,24 @@ > > chosen { > > stdout-path = "serial0:115200n8"; > > }; > >+ > >+ regulator_fixed_3p3: s3300 { > >+ compatible = "regulator-fixed"; > >+ regulator-min-microvolt = <3300000>; > >+ regulator-max-microvolt = <3300000>; > >+ regulator-boot-on; > >+ regulator-always-on; > >+ regulator-name = "fixed_3p3"; > >+ }; > >+ > >+ regulator_fixed_0p925: s0925 { > >+ compatible = "regulator-fixed"; > >+ regulator-min-microvolt = <925000>; > >+ regulator-max-microvolt = <925000>; > >+ regulator-boot-on; > >+ regulator-always-on; > >+ regulator-name = "fixed_0p925"; > >+ }; > > }; > > Let me repeat from v13, so that it is not lost (please excuse me for the > spam): > > Nit: these two regulators are not references from SoC dtsi. So they don't > have to be a part of this commit and can be moved to one of the next commits > (I'd prefer the last one). Sure. Have posted v15 with the suggested changes. Please review. Thanks Varada > > > &blsp1_uart2 { > >diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >index 0baeb10..feabc19 100644 > >--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >@@ -465,6 +465,91 @@ > > status = "disabled"; > > }; > >+ usb_0_qusbphy: phy@7b000 { > >+ compatible = "qcom,ipq9574-qusb2-phy"; > >+ reg = <0x0007b000 0x180>; > >+ #phy-cells = <0>; > >+ > >+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > >+ <&xo_board_clk>; > >+ clock-names = "cfg_ahb", > >+ "ref"; > >+ > >+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > >+ status = "disabled"; > >+ }; > >+ > >+ usb_0_qmpphy: phy@7d000 { > >+ compatible = "qcom,ipq9574-qmp-usb3-phy"; > >+ reg = <0x0007d000 0xa00>; > >+ #phy-cells = <0>; > >+ > >+ clocks = <&gcc GCC_USB0_AUX_CLK>, > >+ <&xo_board_clk>, > >+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > >+ <&gcc GCC_USB0_PIPE_CLK>; > >+ clock-names = "aux", > >+ "ref", > >+ "cfg_ahb", > >+ "pipe"; > >+ > >+ resets = <&gcc GCC_USB0_PHY_BCR>, > >+ <&gcc GCC_USB3PHY_0_PHY_BCR>; > >+ reset-names = "phy", > >+ "phy_phy"; > >+ > >+ #clock-cells = <0>; > >+ clock-output-names = "usb0_pipe_clk"; > >+ > >+ status = "disabled"; > >+ }; > >+ > >+ usb3: usb@8af8800 { > >+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; > >+ reg = <0x08af8800 0x400>; > >+ #address-cells = <1>; > >+ #size-cells = <1>; > >+ ranges; > >+ > >+ clocks = <&gcc GCC_SNOC_USB_CLK>, > >+ <&gcc GCC_USB0_MASTER_CLK>, > >+ <&gcc GCC_ANOC_USB_AXI_CLK>, > >+ <&gcc GCC_USB0_SLEEP_CLK>, > >+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; > >+ > >+ clock-names = "cfg_noc", > >+ "core", > >+ "iface", > >+ "sleep", > >+ "mock_utmi"; > >+ > >+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > >+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; > >+ assigned-clock-rates = <200000000>, > >+ <24000000>; > >+ > >+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; > >+ interrupt-names = "pwr_event"; > >+ > >+ resets = <&gcc GCC_USB_BCR>; > >+ status = "disabled"; > >+ > >+ usb_0_dwc3: usb@8a00000 { > >+ compatible = "snps,dwc3"; > >+ reg = <0x8a00000 0xcd00>; > >+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > >+ clock-names = "ref"; > >+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > >+ phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; > >+ phy-names = "usb2-phy", "usb3-phy"; > >+ tx-fifo-resize; > >+ snps,is-utmi-l1-suspend; > >+ snps,hird-threshold = /bits/ 8 <0x0>; > >+ snps,dis_u2_susphy_quirk; > >+ snps,dis_u3_susphy_quirk; > >+ }; > >+ }; > >+ > > intc: interrupt-controller@b000000 { > > compatible = "qcom,msm-qgic2"; > > reg = <0x0b000000 0x1000>, /* GICD */ > > -- > With best wishes > Dmitry >
This patch series adds the relevant phy and controller configurations for enabling USB on IPQ9754 Portions of the patchset have been merged. Please see https://lore.kernel.org/lkml/ZGN9gchu7dRb6QwC@matsya/ [v14]: - Missed Konrad's comment. Switch order of regulator-boot-on & regulator-always-on in mp5496_l2 node [v13]: - Move fixed regulator definitions from SoC dtsi to board dts - Remove 'dr_mode' from SoC dtsi - Move 'status' property to the end [v12]: - In dtsi usb@8a00000 -> usb@8af8800 [v11]: - Rename dwc_0 -> usb_0_dwc3 - Minor change in qcom,sc8280xp-qmp-usb3-uni-phy.yaml to factor in latest updates to the file [v10]: - Fix regulator definitions - Address couple of other comments [v9]: - Update bindings to make power-domains as optional since IPQ9574 doesn't have GDSCs [v8]: - Update bindings for the clock name change [v7]: - com_aux -> cfg_ahb in patch 7 [v6]: - Incorporated review comments - Resolve make dtbs_check messages - Fixed pcs_usb offset - Board dts file name changed [v5]: - Incorporated review comments - 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml - Move qmp phy DT node to newer specification [v4]: - Incorporated review comments - Address all 'make dtbs_check' errors [v3]: - Incorporated review comments regarding coding style [v2]: - Incorporated review comments regarding coding style, maintaining sorted order of entries and unused phy register offsets - Removed NOC clock entries from DT node (will be implemented later with interconnect support) - Fixed 'make dtbs_check' errors/warnings [v1]: https://lore.kernel.org/linux-arm-msm/5dac3aa4-8dc7-f9eb-5cf3-b361efdc9494@linaro.org/T/ Varadarajan Narayanan (5): dt-bindings: usb: dwc3: Add IPQ9574 compatible clk: qcom: gcc-ipq9574: Add USB related clocks arm64: dts: qcom: ipq9574: Add USB related nodes arm64: dts: qcom: ipq9574: Add LDO regulator node arm64: dts: qcom: ipq9574: Enable USB .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 +- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 48 ++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 ++++++++++++++++++++++ drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 + 5 files changed, 174 insertions(+), 1 deletion(-)