Message ID | cover.1586174566.git.leonard.crestez@nxp.com |
---|---|
Headers | show |
Series | interconnect: Add imx support via devfreq | expand |
On 4/6/20 9:03 PM, Leonard Crestez wrote: > Add initial support for dynamic frequency switching on pieces of the imx > interconnect fabric. > > All this driver does is set a clk rate based on an opp table, it does > not map register areas. > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm> > --- > drivers/devfreq/Kconfig | 8 +++ > drivers/devfreq/Makefile | 1 + > drivers/devfreq/imx-bus.c | 138 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 147 insertions(+) > create mode 100644 drivers/devfreq/imx-bus.c > (snip) Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
On 06.04.20 14:03, Leonard Crestez wrote: > Add nodes for the main interconnect of the imx8m series chips. > > These nodes are bound to by devfreq and interconnect drivers. > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 24 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 +++++++++++++++++++++++ > 3 files changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 175c28ae10cf..41047b6709b6 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -6,10 +6,11 @@ > #include <dt-bindings/clock/imx8mm-clock.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/thermal/thermal.h> > +#include <dt-bindings/interconnect/imx8mm.h> > > #include "imx8mm-pinfunc.h" > > / { > interrupt-parent = <&gic>; > @@ -860,10 +861,33 @@ > status = "disabled"; > }; > > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MM_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-150M { > + opp-hz = /bits/ 64 <150000000>; > + }; > + opp-375M { > + opp-hz = /bits/ 64 <375000000>; > + }; > + opp-750M { > + opp-hz = /bits/ 64 <750000000>; > + }; > + }; > + }; > + > aips4: bus@32c00000 { > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32df0000 0x10000>; > #address-cells = <1>; > #size-cells = <1>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 88e7d74e077f..e8a55956813f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -6,10 +6,11 @@ > #include <dt-bindings/clock/imx8mn-clock.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/thermal/thermal.h> > +#include <dt-bindings/interconnect/imx8mn.h> > > #include "imx8mn-pinfunc.h" > > / { > interrupt-parent = <&gic>; > @@ -751,10 +752,33 @@ > status = "disabled"; > }; > > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MN_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + opp-600M { > + opp-hz = /bits/ 64 <600000000>; > + }; > + opp-800M { > + opp-hz = /bits/ 64 <800000000>; > + }; > + }; > + }; > + > aips4: bus@32c00000 { > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32df0000 0x10000>; > #address-cells = <1>; > #size-cells = <1>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index ea93bc4b7d7e..3a208feec74c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -9,10 +9,11 @@ > #include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include "dt-bindings/input/input.h" > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/thermal/thermal.h> > +#include <dt-bindings/interconnect/imx8mq.h> > #include "imx8mq-pinfunc.h" > > / { > interrupt-parent = <&gpc>; > > @@ -1026,10 +1027,33 @@ > fsl,num-rx-queues = <3>; > status = "disabled"; > }; > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MQ_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-133M { > + opp-hz = /bits/ 64 <133333333>; > + }; > + opp-400M { > + opp-hz = /bits/ 64 <400000000>; > + }; > + opp-800M { > + opp-hz = /bits/ 64 <800000000>; > + }; > + }; > + }; > + > bus@32c00000 { /* AIPS4 */ > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32df0000 0x10000>; > #address-cells = <1>; > #size-cells = <1>; > imx8mq: Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm> martin
Hi, On 4/6/20 15:03, Leonard Crestez wrote: > This series adds interconnect scaling support for imx8m series chips. It uses a > per-SOC interconnect provider layered on top of multiple instances of devfreq > for scalable nodes along the interconnect. > > Existing qcom interconnect providers mostly translate bandwidth requests into > firmware calls but equivalent firmware on imx8m is much thinner. Scaling > support for individual nodes is implemented as distinct devfreq drivers > instead. > > The imx interconnect provider doesn't communicate with devfreq directly > but rather computes "minimum frequencies" for nodes along the path and > creates dev_pm_qos requests. > > Since there is no single devicetree node that can represent the > "interconnect" the main NOC is picked as the "interconnect provider" and > will probe the interconnect platform device if #interconnect-cells is > present. This avoids introducing "virtual" devices but it means that DT > bindings of main NOC includes properties for both devfreq and > interconnect. Thank you for your work Leonard! There is no build dependency between the devfreq and interconnect patches, so i can apply patches 1,4-7. Chanwoo, should i take also the two devfreq patches with your Ack? Thanks, Georgi
Hi, On 4/29/20 4:30 PM, Georgi Djakov wrote: > Hi, > > On 4/6/20 15:03, Leonard Crestez wrote: >> This series adds interconnect scaling support for imx8m series chips. It uses a >> per-SOC interconnect provider layered on top of multiple instances of devfreq >> for scalable nodes along the interconnect. >> >> Existing qcom interconnect providers mostly translate bandwidth requests into >> firmware calls but equivalent firmware on imx8m is much thinner. Scaling >> support for individual nodes is implemented as distinct devfreq drivers >> instead. >> >> The imx interconnect provider doesn't communicate with devfreq directly >> but rather computes "minimum frequencies" for nodes along the path and >> creates dev_pm_qos requests. >> >> Since there is no single devicetree node that can represent the >> "interconnect" the main NOC is picked as the "interconnect provider" and >> will probe the interconnect platform device if #interconnect-cells is >> present. This avoids introducing "virtual" devices but it means that DT >> bindings of main NOC includes properties for both devfreq and >> interconnect. > > Thank you for your work Leonard! There is no build dependency between the > devfreq and interconnect patches, so i can apply patches 1,4-7. > > Chanwoo, should i take also the two devfreq patches with your Ack? As you commented, if there are no build dependency, I think it better to be merged to devfreq.git for the history. I'll apply patch2,3 to devfreq git for v5.8-rc1. Thanks.