| Message ID | 20241101-qcs615-mm-clockcontroller-v2-0-d1a4870a4aed@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform | expand |
On 01/11/2024 10:38, Taniya Das wrote: > + .vco_val = 0x2 << 20, vco_val = BIT(21) > + .vco_mask = 0x3 << 20, Instead of bit shifting couldn't we just use GENMASK ? Aside from anything else shifting a hex value by a decimal value isn't the clearest code in the world. vco_mask = GENMASK(21, 20) Much cleaner. drivers/clk/qcom/gcc-sm6115.c Same comment for all of the bit-shifts in the series, I appreciate the shifts are what the downstream code does but BIT/GENMASK does this job better. Once fixed you can add my Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> to this file --- bod
On 11/1/2024 4:08 PM, Taniya Das wrote: > The alpha PLLs which slew to a new frequency at runtime would require > the PLL to calibrate at the mid point of the VCO. Add the new PLL ops > which can support the slewing of the PLL to a new frequency. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 170 +++++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 1 + > 2 files changed, 171 insertions(+) Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Thanks, Imran
On 11/1/2024 5:59 PM, Bryan O'Donoghue wrote: > On 01/11/2024 10:38, Taniya Das wrote: >> + .vco_val = 0x2 << 20, > > vco_val = BIT(21) > Will fix it in the next patch. >> + .vco_mask = 0x3 << 20, > > Instead of bit shifting couldn't we just use GENMASK ? > > Aside from anything else shifting a hex value by a decimal value isn't > the clearest code in the world. > > vco_mask = GENMASK(21, 20) > > Much cleaner. > > drivers/clk/qcom/gcc-sm6115.c > > Same comment for all of the bit-shifts in the series, I appreciate the > shifts are what the downstream code does but BIT/GENMASK does this job > better. > I agree, will fix it in the next patch. > Once fixed you can add my > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > > to this file
Add support for multimedia clock controllers on Qualcomm QCS615 platform. Update the defconfig to enable these clock controllers. Global clock controller support https://lore.kernel.org/all/20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com/ Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- Changes in v2: - cleanups in clk_alpha_pll_slew_update and clk_alpha_pll_slew_enable functions [Christophe] - update PLL configs for "vco_val = 0x0" shift(20) [Bryan O'Donoghue] - update PLL configs to use lower case for L value [Dmitry] - Link parents for IFE/IPE/BPS GDSCs as Titan Top GDSC [Bryan O'Donoghue, Dmitry] - Remove DT_BI_TCXO_AO from camcc-qcs615 [Dmitry] - Remove HW_CTRL_TRIGGER from camcc-qcs615 [Bryan O'Donoghue] - Update platform name for default configuration [Dmitry] - Link to v1: https://lore.kernel.org/r/20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com --- Taniya Das (11): clk: qcom: Update the support for alpha mode configuration clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Display clock controller clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver dt-bindings: clock: Add Qualcomm QCS615 Video clock controller clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver arm64: defconfig: Enable QCS615 clock controllers .../bindings/clock/qcom,qcs615-camcc.yaml | 60 + .../bindings/clock/qcom,qcs615-dispcc.yaml | 73 + .../bindings/clock/qcom,qcs615-gpucc.yaml | 66 + .../bindings/clock/qcom,qcs615-videocc.yaml | 64 + arch/arm64/configs/defconfig | 4 + drivers/clk/qcom/Kconfig | 35 + drivers/clk/qcom/Makefile | 4 + drivers/clk/qcom/camcc-qcs615.c | 1591 ++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 172 +++ drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/dispcc-qcs615.c | 786 ++++++++++ drivers/clk/qcom/gpucc-qcs615.c | 525 +++++++ drivers/clk/qcom/videocc-qcs615.c | 332 ++++ include/dt-bindings/clock/qcom,qcs615-camcc.h | 110 ++ include/dt-bindings/clock/qcom,qcs615-dispcc.h | 52 + include/dt-bindings/clock/qcom,qcs615-gpucc.h | 39 + include/dt-bindings/clock/qcom,qcs615-videocc.h | 30 + 17 files changed, 3944 insertions(+) --- base-commit: 15e7d45e786a62a211dd0098fee7c57f84f8c681 change-id: 20241016-qcs615-mm-clockcontroller-cff9aea7a006 Best regards,