| Message ID | 20241025030732.29743-1-quic_qqzhou@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support for APPS SMMU on QCS615 | expand |
On Fri, Oct 25, 2024 at 08:37:31AM +0530, Qingqing Zhou wrote: > Add the SCM node for QCS615 platform. It is an interface to > communicate to the secure firmware. > > Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index ac4c4c751da1..027c5125f36b 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -278,6 +278,13 @@ > reg = <0 0x80000000 0 0>; > }; > > + firmware { > + scm { > + compatible = "qcom,scm-qcs615", "qcom,scm"; > + qcom,dload-mode = <&tcsr 0x13000>; No CRYPTO clock? > + }; > + }; > + > camnoc_virt: interconnect-0 { > compatible = "qcom,qcs615-camnoc-virt"; > #interconnect-cells = <2>; > -- > 2.17.1 >
On 25.10.2024 5:07 AM, Qingqing Zhou wrote: > Add the APPS SMMU node for QCS615 platform. Add the dma-ranges > to limit DMA address range to 36bit width to align with system > architecture. > > Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > --- You probably also want to mark it `dma-coherent` (see e.g. x1e80100.dtsi) Konrad
On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: > On 25.10.2024 5:07 AM, Qingqing Zhou wrote: > > Add the APPS SMMU node for QCS615 platform. Add the dma-ranges > > to limit DMA address range to 36bit width to align with system > > architecture. > > > > Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > > --- > > You probably also want to mark it `dma-coherent` (see e.g. > x1e80100.dtsi) Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't marked as such.
On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote: > On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: >> On 25.10.2024 5:07 AM, Qingqing Zhou wrote: >>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>> to limit DMA address range to 36bit width to align with system >>> architecture. >>> >>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>> --- >> >> You probably also want to mark it `dma-coherent` (see e.g. >> x1e80100.dtsi) > > Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't > marked as such. I don't think I have any documentation on this, so.. one way to find out! Konrad
On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote: > On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote: > > On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: > >> On 25.10.2024 5:07 AM, Qingqing Zhou wrote: > >>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges > >>> to limit DMA address range to 36bit width to align with system > >>> architecture. > >>> > >>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > >>> --- > >> > >> You probably also want to mark it `dma-coherent` (see e.g. > >> x1e80100.dtsi) > > > > Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't > > marked as such. > > I don't think I have any documentation on this, so.. one way to find out! I don't have qcs615 at hand, so a purely theoretical question. But how should it break if we mark it as dma-coherent, while it is not?
On 26.10.2024 8:18 PM, Dmitry Baryshkov wrote: > On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote: >> On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote: >>> On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: >>>> On 25.10.2024 5:07 AM, Qingqing Zhou wrote: >>>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>>>> to limit DMA address range to 36bit width to align with system >>>>> architecture. >>>>> >>>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>>>> --- >>>> >>>> You probably also want to mark it `dma-coherent` (see e.g. >>>> x1e80100.dtsi) >>> >>> Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't >>> marked as such. >> >> I don't think I have any documentation on this, so.. one way to find out! > > I don't have qcs615 at hand, so a purely theoretical question. But how > should it break if we mark it as dma-coherent, while it is not? The board will hang rather quickly Konrad
On Fri, 25 Oct 2024 08:37:28 +0530, Qingqing Zhou wrote: > Enable APPS SMMU function on QCS615 platform. APPS SMMU is required > for address translation in devices including Ethernet/UFS/USB and > so on. > > Add the SCM node for SMMU probing normally. SMMU driver probe will > check qcom_scm ready or not, without SCM node, SMMU driver probe will > defer. > The dmesg log without SCM node: > platform 15000000.iommu: deferred probe pending: arm-smmu: qcom_scm not ready > > [...] Applied SMMU bindings change to will (for-joerg/arm-smmu/bindings), thanks! [2/4] dt-bindings: arm-smmu: document QCS615 APPS SMMU https://git.kernel.org/will/c/515c8ff024ba Cheers,
在 10/28/2024 11:46 PM, Konrad Dybcio 写道: > On 26.10.2024 8:18 PM, Dmitry Baryshkov wrote: >> On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote: >>> On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote: >>>> On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: >>>>> On 25.10.2024 5:07 AM, Qingqing Zhou wrote: >>>>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>>>>> to limit DMA address range to 36bit width to align with system >>>>>> architecture. >>>>>> >>>>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>>>>> --- >>>>> >>>>> You probably also want to mark it `dma-coherent` (see e.g. >>>>> x1e80100.dtsi) >>>> >>>> Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't >>>> marked as such. >>> >>> I don't think I have any documentation on this, so.. one way to find out! >> >> I don't have qcs615 at hand, so a purely theoretical question. But how >> should it break if we mark it as dma-coherent, while it is not? > > The board will hang rather quickly > > Konrad Thanks for review comments from Konrad and Dmitry! QCS615 SMMU hardware supports IO-coherency after confirming with Qualcomm hardware team. We also try to add "dma-coherent" for APPS SMMU node and test some SMMU clients, such as UFS and Ethernet, these SMMU clients work well on QCS615. Do you advise and agree to add "dma-coherent" for SMMU node?
在 10/25/2024 2:02 PM, Dmitry Baryshkov 写道: > On Fri, Oct 25, 2024 at 08:37:31AM +0530, Qingqing Zhou wrote: >> Add the SCM node for QCS615 platform. It is an interface to >> communicate to the secure firmware. >> >> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index ac4c4c751da1..027c5125f36b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -278,6 +278,13 @@ >> reg = <0 0x80000000 0 0>; >> }; >> >> + firmware { >> + scm { >> + compatible = "qcom,scm-qcs615", "qcom,scm"; >> + qcom,dload-mode = <&tcsr 0x13000>; > > No CRYPTO clock? NO, response from Qualcomm clock team is "the current QCS615 RPMH code does not have the clock support for CE clock", so we don't configure clocks here. > >> + }; >> + }; >> + >> camnoc_virt: interconnect-0 { >> compatible = "qcom,qcs615-camnoc-virt"; >> #interconnect-cells = <2>; >> -- >> 2.17.1 >> >
On Wed, Oct 30, 2024 at 04:42:19PM +0800, Qingqing Zhou wrote: > > > 在 10/25/2024 2:02 PM, Dmitry Baryshkov 写道: > > On Fri, Oct 25, 2024 at 08:37:31AM +0530, Qingqing Zhou wrote: > >> Add the SCM node for QCS615 platform. It is an interface to > >> communicate to the secure firmware. > >> > >> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > >> --- > >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++ > >> 1 file changed, 7 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > >> index ac4c4c751da1..027c5125f36b 100644 > >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > >> @@ -278,6 +278,13 @@ > >> reg = <0 0x80000000 0 0>; > >> }; > >> > >> + firmware { > >> + scm { > >> + compatible = "qcom,scm-qcs615", "qcom,scm"; > >> + qcom,dload-mode = <&tcsr 0x13000>; > > > > No CRYPTO clock? > NO, response from Qualcomm clock team is "the current QCS615 RPMH code does not have the clock support for CE clock", so we don't configure clocks here. Is this going to change in future? > > > >> + }; > >> + }; > >> + > >> camnoc_virt: interconnect-0 { > >> compatible = "qcom,qcs615-camnoc-virt"; > >> #interconnect-cells = <2>; > >> -- > >> 2.17.1 > >> > > >
在 11/1/2024 2:59 AM, Dmitry Baryshkov 写道: > On Wed, Oct 30, 2024 at 04:42:19PM +0800, Qingqing Zhou wrote: >> >> >> 在 10/25/2024 2:02 PM, Dmitry Baryshkov 写道: >>> On Fri, Oct 25, 2024 at 08:37:31AM +0530, Qingqing Zhou wrote: >>>> Add the SCM node for QCS615 platform. It is an interface to >>>> communicate to the secure firmware. >>>> >>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> index ac4c4c751da1..027c5125f36b 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> @@ -278,6 +278,13 @@ >>>> reg = <0 0x80000000 0 0>; >>>> }; >>>> >>>> + firmware { >>>> + scm { >>>> + compatible = "qcom,scm-qcs615", "qcom,scm"; >>>> + qcom,dload-mode = <&tcsr 0x13000>; >>> >>> No CRYPTO clock? >> NO, response from Qualcomm clock team is "the current QCS615 RPMH code does not have the clock support for CE clock", so we don't configure clocks here. > > Is this going to change in future? NO, from Qualcomm clock team, the clock/BW is handled internally in our trustzone and do not see any requirement change going forward to move the clocks/BW vote to HLOS driver. > >>> >>>> + }; >>>> + }; >>>> + >>>> camnoc_virt: interconnect-0 { >>>> compatible = "qcom,qcs615-camnoc-virt"; >>>> #interconnect-cells = <2>; >>>> -- >>>> 2.17.1 >>>> >>> >> >
On Mon, Nov 04, 2024 at 03:36:37PM +0800, Qingqing Zhou wrote: > > > 在 11/1/2024 2:59 AM, Dmitry Baryshkov 写道: > > On Wed, Oct 30, 2024 at 04:42:19PM +0800, Qingqing Zhou wrote: > >> > >> > >> 在 10/25/2024 2:02 PM, Dmitry Baryshkov 写道: > >>> On Fri, Oct 25, 2024 at 08:37:31AM +0530, Qingqing Zhou wrote: > >>>> Add the SCM node for QCS615 platform. It is an interface to > >>>> communicate to the secure firmware. > >>>> > >>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > >>>> --- > >>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 7 +++++++ > >>>> 1 file changed, 7 insertions(+) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > >>>> index ac4c4c751da1..027c5125f36b 100644 > >>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > >>>> @@ -278,6 +278,13 @@ > >>>> reg = <0 0x80000000 0 0>; > >>>> }; > >>>> > >>>> + firmware { > >>>> + scm { > >>>> + compatible = "qcom,scm-qcs615", "qcom,scm"; > >>>> + qcom,dload-mode = <&tcsr 0x13000>; > >>> > >>> No CRYPTO clock? > >> NO, response from Qualcomm clock team is "the current QCS615 RPMH code does not have the clock support for CE clock", so we don't configure clocks here. > > > > Is this going to change in future? > NO, from Qualcomm clock team, the clock/BW is handled internally in our trustzone and do not see any requirement change going forward to move the clocks/BW vote to HLOS driver. Nit: please wrap your replies at some sensible line length (72-75 chars). Normal email clients do that for you. For the patch itself: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > >>> > >>>> + }; > >>>> + }; > >>>> + > >>>> camnoc_virt: interconnect-0 { > >>>> compatible = "qcom,qcs615-camnoc-virt"; > >>>> #interconnect-cells = <2>; > >>>> -- > >>>> 2.17.1 > >>>> > >>> > >> > > >