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[v2,0/4] add NETCMIX block control support on i.MX95

Message ID 20240710084345.2016687-1-wei.fang@nxp.com
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Series add NETCMIX block control support on i.MX95 | expand

Message

Wei Fang July 10, 2024, 8:43 a.m. UTC 
The NETCMIX block control consists of registers for configuration of
peripherals in the NETC domain, such as MQS, SAI and NETC. So add the
NETCMIX block control support on i.MX95 platform.

---
V2:
1. Patch 2 is new patch.
2. Add rmii reference clock mux for ENETC0 and ENETC1 in patch 3.
Link to V1: https://lore.kernel.org/all/20240709073603.1967609-3-wei.fang@nxp.com/
---

Wei Fang (4):
  dt-bindings: clock: add i.MX95 NETCMIX block control
  dt-bindings: clock: add RMII clock selection
  clk: imx95: enable the clock of NETCMIX block control
  arm64: dts: imx95: Add NETCMIX block control support

 .../bindings/clock/nxp,imx95-blk-ctl.yaml     |  1 +
 arch/arm64/boot/dts/freescale/imx95.dtsi      | 12 ++++++++
 drivers/clk/imx/clk-imx95-blk-ctl.c           | 30 +++++++++++++++++++
 include/dt-bindings/clock/nxp,imx95-clock.h   |  3 ++
 4 files changed, 46 insertions(+)

Comments

Peng Fan July 18, 2024, 7:35 a.m. UTC | #1 
> Subject: [PATCH v2 3/4] clk: imx95: enable the clock of NETCMIX block
> control
> 
> The NETCMIX block control consists of registers for configuration of
> peripherals in the NETC domain, so enable the clock of NETCMIX to
> support the configuration.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2:
> Add RMII reference clock mux for ENETC0 and ENETC1.
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 30
> +++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-
> imx95-blk-ctl.c
> index 74f595f9e5e3..19a62da74be4 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -248,6 +248,35 @@ static const struct imx95_blk_ctl_dev_data
> dispmix_csr_dev_data = {
>  	.clk_reg_offset = 0,
>  };
> 
> +static const struct imx95_blk_ctl_clk_dev_data
> netxmix_clk_dev_data[] = {
> +	[IMX95_CLK_NETCMIX_ENETC0_RMII] = {
> +		.name = "enetc0_rmii_sel",
> +		.parent_names = (const char *[]){"ext_enetref",
> "enetref"},
> +		.num_parents = 2,
> +		.reg = 4,
> +		.bit_idx = 5,
> +		.bit_width = 1,
> +		.type = CLK_MUX,
> +		.flags = CLK_SET_RATE_NO_REPARENT |
> CLK_SET_RATE_PARENT,
> +	},
> +	[IMX95_CLK_NETCMIX_ENETC1_RMII] = {
> +		.name = "enetc1_rmii_sel",
> +		.parent_names = (const char *[]){"ext_enetref",
> "enetref"},
> +		.num_parents = 2,
> +		.reg = 4,

Both the entry use reg address 4, use a lock to protect?

Regards,
Peng.

> +		.bit_idx = 10,
> +		.bit_width = 1,
> +		.type = CLK_MUX,
> +		.flags = CLK_SET_RATE_NO_REPARENT |
> CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
> +	.num_clks = ARRAY_SIZE(netxmix_clk_dev_data),
> +	.clk_dev_data = netxmix_clk_dev_data,
> +	.clk_reg_offset = 0,
> +};
> +
>  static int imx95_bc_probe(struct platform_device *pdev)  {
>  	struct device *dev = &pdev->dev;
> @@ -419,6 +448,7 @@ static const struct of_device_id
> imx95_bc_of_match[] = {
>  	{ .compatible = "nxp,imx95-lvds-csr", .data =
> &lvds_csr_dev_data },
>  	{ .compatible = "nxp,imx95-display-csr", .data =
> &dispmix_csr_dev_data },
>  	{ .compatible = "nxp,imx95-vpu-csr", .data =
> &vpublk_dev_data },
> +	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data =
> +&netcmix_dev_data},
>  	{ /* Sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
> --
> 2.34.1
Wei Fang July 18, 2024, 8 a.m. UTC | #2 
> -----Original Message-----
> From: Peng Fan <peng.fan@nxp.com>
> Sent: 2024年7月18日 15:35
> To: Wei Fang <wei.fang@nxp.com>; mturquette@baylibre.com;
> sboyd@kernel.org; robh@kernel.org; conor+dt@kernel.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com;
> abelvesa@kernel.org
> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v2 3/4] clk: imx95: enable the clock of NETCMIX block
> control
> 
> > Subject: [PATCH v2 3/4] clk: imx95: enable the clock of NETCMIX block
> > control
> >
> > The NETCMIX block control consists of registers for configuration of
> > peripherals in the NETC domain, so enable the clock of NETCMIX to
> > support the configuration.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> > V2:
> > Add RMII reference clock mux for ENETC0 and ENETC1.
> > ---
> >  drivers/clk/imx/clk-imx95-blk-ctl.c | 30
> > +++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > b/drivers/clk/imx/clk- imx95-blk-ctl.c index
> > 74f595f9e5e3..19a62da74be4 100644
> > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > @@ -248,6 +248,35 @@ static const struct imx95_blk_ctl_dev_data
> > dispmix_csr_dev_data = {
> >  	.clk_reg_offset = 0,
> >  };
> >
> > +static const struct imx95_blk_ctl_clk_dev_data
> > netxmix_clk_dev_data[] = {
> > +	[IMX95_CLK_NETCMIX_ENETC0_RMII] = {
> > +		.name = "enetc0_rmii_sel",
> > +		.parent_names = (const char *[]){"ext_enetref",
> > "enetref"},
> > +		.num_parents = 2,
> > +		.reg = 4,
> > +		.bit_idx = 5,
> > +		.bit_width = 1,
> > +		.type = CLK_MUX,
> > +		.flags = CLK_SET_RATE_NO_REPARENT |
> > CLK_SET_RATE_PARENT,
> > +	},
> > +	[IMX95_CLK_NETCMIX_ENETC1_RMII] = {
> > +		.name = "enetc1_rmii_sel",
> > +		.parent_names = (const char *[]){"ext_enetref",
> > "enetref"},
> > +		.num_parents = 2,
> > +		.reg = 4,
> 
> Both the entry use reg address 4, use a lock to protect?
> 

I think there is already a lock (bc->lock) to protect it, right?
if (data->type == CLK_MUX) {
			hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
					data->num_parents, data->flags, reg,
					data->bit_idx, data->bit_width,
					data->flags2, &bc->lock);
}

Or did I misunderstand the usage of bc->lock?
Peng Fan July 19, 2024, 5:07 a.m. UTC | #3 
> Subject: [PATCH v2 3/4] clk: imx95: enable the clock of NETCMIX block
> control
> 
> The NETCMIX block control consists of registers for configuration of
> peripherals in the NETC domain, so enable the clock of NETCMIX to
> support the configuration.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Wei Fang July 22, 2024, 1:58 a.m. UTC | #4 
> -----Original Message-----
> From: Wei Fang
> Sent: 2024年7月10日 16:57
> To: mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de;
> festevam@gmail.com; abelvesa@kernel.org; Peng Fan <peng.fan@nxp.com>
> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: [PATCH v2 4/4] arm64: dts: imx95: Add NETCMIX block control
> support
> 
> Add NETCMIX block control support.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2:
> no changes.
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi
> b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 1bbf9a0468f6..6e86aa98b431 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1188,5 +1188,17 @@ pcie1_ep: pcie-ep@4c380000 {
>  			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
>  			status = "disabled";
>  		};
> +
> +		netcmix_blk_ctrl: syscon@4c810000 {
> +			compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon";
> +			reg = <0x0 0x4c810000 0x0 0x10000>;
> +			#clock-cells = <1>;
> +			clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
> +			assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>;
> +			assigned-clock-parents = <&scmi_clk
> IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> +			assigned-clock-rates = <133333333>;
> +			power-domains = <&scmi_devpd IMX95_PD_NETC>;
> +			status = "disabled";
> +		};
>  	};
>  };
> --
> 2.34.1

Kindly ping...