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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5b29015a3dbsm321132eaf.46.2024.05.10.17.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 17:49:55 -0700 (PDT) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: David Lechner , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH RFC v2 0/8] spi: axi-spi-engine: add offload support Date: Fri, 10 May 2024 19:44:23 -0500 Message-ID: <20240510-dlech-mainline-spi-engine-offload-2-v2-0-8707a870c435@baylibre.com> X-Mailer: git-send-email 2.43.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 Continuing the discussion started a few months ago [1]... It was suggested that we were trying to do too much in one series. So we split out part of the series into a separate series that adds generic support for pre-preparing SPI messages [2]. That work has been merged. [1]: https://lore.kernel.org/linux-spi/20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com/ [2]: https://lore.kernel.org/linux-spi/20240219-mainline-spi-precook-message-v2-0-4a762c6701b9@baylibre.com/ I was hoping to also break down the remaining work into smaller parts by first only considering more generic offload support that could be used with the regular SPI message queue and leaving out the hardware trigger bits. But the hardware I have at hand is not capable of doing that so this is the best I can do for now. (Happy to take suggestions if someone knows some other hardware that could be used for this.) There have been significant changes since the last version so I'll discuss what changed in each patch instead of having a very lengthy cover letter. A working branch complete with extra hacks can be found at [3]. [3]: https://github.com/dlech/linux/tree/axi-spi-engine-offload-v2 --- As a recap, here is the background and end goal of this series: The AXI SPI Engine is a SPI controller that has the ability to record a series of SPI transactions and then play them back using a hardware trigger. This allows operations to be performed, repeating many times, without any CPU intervention. This is needed for achieving high data rates (millions of samples per second) from ADCs and DACs that are connected via a SPI bus. The offload hardware interface consists of a trigger input and a data output for the RX data. These are connected to other hardware external to the SPI controller. To record one or more transactions, commands and TX data are written to memories in the controller (RX buffer is not used since RX data gets piped to an external sink). This sequence of transactions can then be played back when the trigger input is asserted. This series includes core SPI support along with the first SPI controller (AXI SPI Engine) and SPI peripheral (AD7944 ADC) that use them. This enables capturing analog data at 2 million samples per second. The hardware setup looks like this: +-------------------------------+ +------------------+ | | | | | SOC/FPGA | | AD7944 ADC | | +---------------------+ | | | | | AXI SPI Engine | | | | | | SPI Bus ============ SPI Bus | | | | | | | | | +---------------+ | | | | | | | Offload 0 | | | +------------------+ | | | RX DATA OUT > > > > | | | | TRIGGER IN < < < v | | | +---------------+ | ^ v | | +---------------------+ ^ v | | | AXI PWM | ^ v | | | CH0 > ^ v | | +---------------------+ v | | | AXI DMA | v | | | CH0 < < < | | +---------------------+ | | | +-------------------------------+ To: Mark Brown To: Jonathan Cameron To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Nuno Sá Cc: Michael Hennerich Cc: Lars-Peter Clausen Cc: David Jander Cc: Martin Sperl Cc: Cc: Cc: Cc: --- David Lechner (8): spi: dt-bindings: spi-peripheral-props: add spi-offloads property spi: add basic support for SPI offloading spi: add support for hardware triggered offload spi: add offload xfer flags spi: dt-bindings: axi-spi-engine: document spi-offloads spi: axi-spi-engine: add offload support dt-bindings: iio: adc: adi,ad7944: add SPI offload properties iio: adc: ad7944: add support for SPI offload .../devicetree/bindings/iio/adc/adi,ad7944.yaml | 58 +++++ .../bindings/spi/adi,axi-spi-engine.yaml | 14 ++ .../bindings/spi/spi-peripheral-props.yaml | 10 + drivers/iio/adc/ad7944.c | 147 +++++++++--- drivers/spi/spi-axi-spi-engine.c | 267 ++++++++++++++++++++- drivers/spi/spi.c | 202 +++++++++++++++- include/linux/spi/spi.h | 84 +++++++ 7 files changed, 741 insertions(+), 41 deletions(-) --- base-commit: 14fde009028126f91c2bd72c404e425cf4f8aec3 change-id: 20240510-dlech-mainline-spi-engine-offload-2-afce3790b5ab Best regards,