| Message ID | 20240429111537.2369227-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Enable UFS on gs101 / Pixel 6 (Oriole) | expand |
On 29/04/2024 13:15, Peter Griffin wrote: > This has some configuration bits such as sharability that > are required by UFS. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > Reviewed-by: André Draszik <andre.draszik@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index 38ac4fb1397e..09044deede63 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { > clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; > }; Does not apply anymore, please rebase. Best regards, Krzysztof
On 29/04/2024 13:15, Peter Griffin wrote: > + ufs_0: ufs@14700000 { > + compatible = "google,gs101-ufs"; > + reg = <0x14700000 0x200>, > + <0x14701100 0x200>, > + <0x14780000 0xa000>, > + <0x14600000 0x100>; > + reg-names = "hci", "vs_hci", "unipro", "ufsp"; > + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; > + clock-names = "core_clk", "sclk_unipro_main", "fmp", > + "aclk", "pclk", "sysreg"; > + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; > + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; > + pinctrl-names = "default"; > + phys = <&ufs_0_phy>; > + phy-names = "ufs-phy"; > + samsung,sysreg = <&sysreg_hsi2 0x710>; > + status = "disabled"; > + }; > + > + ufs_0_phy: phy@0x14704000 { Drop 0x from unit address. Best regards, Krzysztof
Hi Krzysztof, On Mon, 29 Apr 2024 at 18:30, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 29/04/2024 13:15, Peter Griffin wrote: > > + ufs_0: ufs@14700000 { > > + compatible = "google,gs101-ufs"; > > + reg = <0x14700000 0x200>, > > + <0x14701100 0x200>, > > + <0x14780000 0xa000>, > > + <0x14600000 0x100>; > > + reg-names = "hci", "vs_hci", "unipro", "ufsp"; > > + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, > > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, > > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, > > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, > > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, > > + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; > > + clock-names = "core_clk", "sclk_unipro_main", "fmp", > > + "aclk", "pclk", "sysreg"; > > + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; > > + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; > > + pinctrl-names = "default"; > > + phys = <&ufs_0_phy>; > > + phy-names = "ufs-phy"; > > + samsung,sysreg = <&sysreg_hsi2 0x710>; > > + status = "disabled"; > > + }; > > + > > + ufs_0_phy: phy@0x14704000 { > > Drop 0x from unit address. Thanks for the review, will fix. Peter
Hi Krzysztof, This series contains the dts, dtsi and sysreg bindings that enables UFS on Pixel 6 (Oriole). From v3 onwards it has been split into separate series as you requested. Along with the various driver code UFS is now functional, the SKhynix HN8T05BZGKX015 can be enumerated, partitions mounted etc. UFS bindings in this series are proposed: https://lore.kernel.org/linux-arm-kernel/20240426122004.2249178-1-peter.griffin@linaro.org/ Clock cmu_hsi2 bindings are proposed: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-0-2157da8b63e3@linaro.org UFS phy bindings used here are already queued by Vinod kind regards, Peter. lore v3: https://lore.kernel.org/lkml/20240426122004.2249178-1-peter.griffin@linaro.org/ lore v2: https://lore.kernel.org/linux-kernel/20240423205006.1785138-1-peter.griffin@linaro.org/ lore v1: https://lore.kernel.org/linux-clk/20240404122559.898930-1-peter.griffin@linaro.org/ Changes since v3: - Fix unit address ordering in gs101.dtsi (Krzysztof) Changes since v2: - Split into separate subsystem series - Split dts and dtsi patches (Krzysztof) Changes since v1: - Collect up tags - fix google,gs101-hsi2-sysreg size (0x10000 not 0x1000) (Andre) - use GPIO defines in DT and add TODO pmic comment (Krzysztof) - Add sysreg clock to ufs node (Andre) Peter Griffin (4): dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible arm64: dts: exynos: gs101: Add the hsi2 sysreg node arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator .../soc/samsung/samsung,exynos-sysreg.yaml | 2 + .../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 42 +++++++++++++++++++ 3 files changed, 62 insertions(+)