| Message ID | 20240422205053.496095-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add IAX45 support for RZ/Five SoC | expand |
Hi Prabhakar, On Mon, Apr 22, 2024 at 10:51 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > The IX45 block on the RZ/Five SoC has additional mask registers > (NMSK/IMSK/TMSK) compared to the RZ/G2L (family) SoC. > > A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function > pointers for irq_(un)mask and irq_(dis/en)able handle the (un)masking > of the interrupts. The irq_chip pointer is now passed as an init callback > and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v2->v3 > - Added RZ/Five specific irqchip instead of polluting the functions > - Fixed review comments pointed by Biju and Geert > - Updated commit message > - moved locking respective read/write functions Thanks for the update! > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -138,6 +142,113 @@ static void rzg2l_irqc_eoi(struct irq_data *d) > irq_chip_eoi_parent(d); > } > > +static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, > + unsigned int hwirq) > +{ > + u32 bit = BIT(hwirq - IRQC_IRQ_START); > + > + raw_spin_lock(&priv->lock); I think you best move the locking to the callers that really need it... > + writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK); > + raw_spin_unlock(&priv->lock); > +} > +static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) > +{ > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > + unsigned int hwirq = irqd_to_hwirq(d); > + > + if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { > + u32 offset = hwirq - IRQC_TINT_START; > + u32 tssr_offset = TSSR_OFFSET(offset); > + u8 tssr_index = TSSR_INDEX(offset); > + u32 reg; > + > + if (enable) > + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); > + else > + rzfive_irqc_mask_tint_interrupt(priv, hwirq); ... else you will do a lock/unlock here, followed by another one below. > + raw_spin_lock(&priv->lock); > + reg = readl_relaxed(priv->base + TSSR(tssr_index)); > + if (enable) > + reg |= TIEN << TSSEL_SHIFT(tssr_offset); > + else > + reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); > + writel_relaxed(reg, priv->base + TSSR(tssr_index)); > + raw_spin_unlock(&priv->lock); > + } else { > + if (enable) > + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); > + else > + rzfive_irqc_mask_irq_interrupt(priv, hwirq); > + } > +} > @@ -401,7 +529,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > return 0; > } > > -static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > +static int rzg2l_irqc_init_helper(struct device_node *node, struct device_node *parent, rzg2l_irqc_common_init()? > + const struct irq_chip *irq_chip) > { > struct irq_domain *irq_domain, *parent_domain; > struct platform_device *pdev; The rest LGTM, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Wed, Apr 24, 2024 at 3:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Apr 22, 2024 at 10:51 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > The IX45 block on the RZ/Five SoC has additional mask registers > > (NMSK/IMSK/TMSK) compared to the RZ/G2L (family) SoC. > > > > A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function > > pointers for irq_(un)mask and irq_(dis/en)able handle the (un)masking > > of the interrupts. The irq_chip pointer is now passed as an init callback > > and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v2->v3 > > - Added RZ/Five specific irqchip instead of polluting the functions > > - Fixed review comments pointed by Biju and Geert > > - Updated commit message > > - moved locking respective read/write functions > > Thanks for the update! > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > > @@ -138,6 +142,113 @@ static void rzg2l_irqc_eoi(struct irq_data *d) > > irq_chip_eoi_parent(d); > > } > > > > +static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, > > + unsigned int hwirq) > > +{ > > + u32 bit = BIT(hwirq - IRQC_IRQ_START); > > + > > + raw_spin_lock(&priv->lock); > > I think you best move the locking to the callers that really need it... > Ok, will do. > > + writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK); > > + raw_spin_unlock(&priv->lock); > > +} > > > +static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) > > +{ > > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > > + unsigned int hwirq = irqd_to_hwirq(d); > > + > > + if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { > > + u32 offset = hwirq - IRQC_TINT_START; > > + u32 tssr_offset = TSSR_OFFSET(offset); > > + u8 tssr_index = TSSR_INDEX(offset); > > + u32 reg; > > + > > + if (enable) > > + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); > > + else > > + rzfive_irqc_mask_tint_interrupt(priv, hwirq); > > ... else you will do a lock/unlock here, followed by another one below. > and move the above code into the lock below. Cheers, Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found on the RZ/G2L family of SoCs. IAX45 performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral interrupts output by each module. And it notifies the interrupt to the PLIC. - Select 32 TINT from 82 GPIOINT. - Integration of bus error interrupts from system bus. - Integration of ECC error interrupts from On-chip RAM. - Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt and integrated ECC error interrupt) - Setting of interrupt detection method. (NMI, IRQ and TINT) - All interrupts are masked by INTMASK. - Mask function for NMI, IRQ and TINT This patch series adds support for IAX45 in the IRQC driver and enables this on RZ/Five SoC. v2->v3 * DTS/I patches dropped from the series as they have been merged into renesas-soc tree * Just using a const from compat string instead of having it in a items * Added RZ/Five specific irqchip v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC irqchip/renesas-rzg2l: Add support for RZ/Five SoC .../renesas,rzg2l-irqc.yaml | 17 +- drivers/irqchip/irq-renesas-rzg2l.c | 150 +++++++++++++++++- 2 files changed, 157 insertions(+), 10 deletions(-)