| Message ID | 20231214150414.1849058-1-enachman@marvell.com |
|---|---|
| Headers | show |
| Series | watchdog: sbsa_gwdt: add support for Marvell ac5 | expand |
On 14/12/2023 16:04, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add watchdog nodes to ac5 and ac5x device tree files > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 14 ++++++++++++++ > arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 8 ++++++++ > 2 files changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index b5e042b8e929..e898c6bd31f0 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -307,6 +307,20 @@ nand: nand-controller@805b0000 { > status = "disabled"; > }; > > +/* > + * Global Watchdog: > + */ Messed indentation. Also unnecessary line breaks around comment, unless you have some KPI per lines of code. If it is the only watchdog, why even commenting on it? > + watchdog: watchdog@80216000 { > + compatible = "marvell,ac5-wd"; > + reg = <0x0 0x80216000 0 0x1000>, > + <0x0 0x80215000 0 0x1000>, > + <0x0 0x80210000 0 0x1000>, > + <0x0 0x7f900000 0 0x1000>, > + <0x0 0x840F8000 0 0x1000>; Lowercase hex. Best regards, Krzysztof
On 14/12/2023 16:04, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add support for Marvell ac5/x variant of the ARM > sbsa global watchdog. This watchdog deviates from > the standard driver by the following items: > > 1. Registers reside in secure register section. > hence access is only possible via SMC calls to ATF. > > 2. There are couple more registers which reside in > other register areas, which needs to be configured > in order for the watchdog to properly generate > reset through the SOC. > > The new Marvell compatibility string differentiates between > the original sbsa mode of operation and the Marvell mode of > operation. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- ... > gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); > if (!gwdt) > return -ENOMEM; > platform_set_drvdata(pdev, gwdt); > > - cf_base = devm_platform_ioremap_resource(pdev, 0); > - if (IS_ERR(cf_base)) > - return PTR_ERR(cf_base); > - > - rf_base = devm_platform_ioremap_resource(pdev, 1); > - if (IS_ERR(rf_base)) > - return PTR_ERR(rf_base); > + if (of_device_is_compatible(np, "marvell,ac5-wd")) { No, use match data. That's its purpose, don't put comaptibles inside code. > + marvell = true; > + gwdt->soc_reg_ops = &smc_reg_ops; > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (IS_ERR(res)) > + return PTR_ERR(res); > + cf_base = res->start; Why do you use entirely different code? > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (IS_ERR(res)) > + return PTR_ERR(res); > + rf_base = res->start; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + if (IS_ERR(res)) > + return PTR_ERR(res); > + cpu_ctrl_base = res->start; > + mng_base = devm_platform_ioremap_resource(pdev, 3); > + if (IS_ERR(mng_base)) > + return PTR_ERR(mng_base); > + rst_ctrl_base = devm_platform_ioremap_resource(pdev, 4); > + if (IS_ERR(rst_ctrl_base)) > + return PTR_ERR(rst_ctrl_base); > + } else { > + gwdt->soc_reg_ops = &direct_reg_ops; > + cf_base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(cf_base)) > + return PTR_ERR(cf_base); Why? This is shared. > + > + rf_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(rf_base)) > + return PTR_ERR(rf_base); Ditto > + } > > /* > * Get the frequency of system counter from the cp15 interface of ARM > @@ -299,7 +482,7 @@ static int sbsa_gwdt_probe(struct platform_device *pdev) > else > wdd->max_hw_heartbeat_ms = GENMASK_ULL(47, 0) / gwdt->clk * 1000; > > - status = readl(cf_base + SBSA_GWDT_WCS); > + status = gwdt->soc_reg_ops->reg_read32(cf_base + SBSA_GWDT_WCS); > if (status & SBSA_GWDT_WCS_WS1) { > dev_warn(dev, "System reset by WDT.\n"); > wdd->bootstatus |= WDIOF_CARDRESET; > @@ -317,7 +500,7 @@ static int sbsa_gwdt_probe(struct platform_device *pdev) > * In case there is a pending ws0 interrupt, just ping > * the watchdog before registering the interrupt routine > */ > - writel(0, rf_base + SBSA_GWDT_WRR); > + gwdt->soc_reg_ops->reg_write32(0, rf_base + SBSA_GWDT_WRR); > if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0, > pdev->name, gwdt)) { > action = 0; > @@ -347,7 +530,28 @@ static int sbsa_gwdt_probe(struct platform_device *pdev) > ret = devm_watchdog_register_device(dev, wdd); > if (ret) > return ret; > - > + /* > + * Marvell AC5/X/IM: need to configure the watchdog > + * HW to trigger reset on WS1 (Watchdog Signal 1): > + * > + * 1. Configure the watchdog signal enable (routing) > + * according to configuration > + * 2. Unmask the wd_rst input signal to the reset unit > + */ > + if (marvell) { > + gwdt->soc_reg_ops->reg_write32(reset, cpu_ctrl_base + > + SBSA_GWDT_MARVELL_CPU_WD_RST_EN_REG); > + id = readl(mng_base + SBSA_GWDT_MARVELL_MNG_ID_REG) & > + SBSA_GWDT_MARVELL_ID_MASK; > + > + if (id == SBSA_GWDT_MARVELL_AC5_ID) > + val = SBSA_GWDT_MARVELL_AC5_RST_UNIT_WD_BIT; > + else > + val = SBSA_GWDT_MARVELL_IRONMAN_RST_UNIT_WD_BIT; > + > + writel(readl(rst_ctrl_base + SBSA_GWDT_MARVELL_RST_CTRL_REG) & ~val, > + rst_ctrl_base + SBSA_GWDT_MARVELL_RST_CTRL_REG); > + } > dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n", > wdd->timeout, gwdt->clk, action, > status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); > @@ -383,6 +587,7 @@ static const struct dev_pm_ops sbsa_gwdt_pm_ops = { > > static const struct of_device_id sbsa_gwdt_of_match[] = { > { .compatible = "arm,sbsa-gwdt", }, > + { .compatible = "marvell,ac5-wd", }, > {}, > }; > MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); Best regards, Krzysztof
On 15/12/23 04:04, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add support for Marvell ac5/x variant of the ARM > sbsa global watchdog. This watchdog deviates from > the standard driver by the following items: > > 1. Registers reside in secure register section. > hence access is only possible via SMC calls to ATF. > > 2. There are couple more registers which reside in > other register areas, which needs to be configured > in order for the watchdog to properly generate > reset through the SOC. > > The new Marvell compatibility string differentiates between > the original sbsa mode of operation and the Marvell mode of > operation. I gave this a quick try on our AC5X based board and it worked well with both action=0/action=1 > Elad Nachman (3): > dt-bindings: watchdog: add Marvell AC5 watchdog > arm64: dts: ac5: add watchdog nodes > watchdog: sbsa_gwdt: add support for Marvell ac5 > > .../bindings/watchdog/arm,sbsa-gwdt.yaml | 52 +++- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 14 + > arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 8 + > drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++-- > 4 files changed, 298 insertions(+), 23 deletions(-) >
On Thu, Dec 14, 2023 at 05:04:11PM +0200, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add support for Marvell ac5/x variant of the ARM > sbsa global watchdog. This watchdog deviates from > the standard driver by the following items: > > 1. Registers reside in secure register section. > hence access is only possible via SMC calls to ATF. Oops. > 2. There are couple more registers which reside in > other register areas, which needs to be configured > in order for the watchdog to properly generate > reset through the SOC. Your firmware should configure these. > > The new Marvell compatibility string differentiates between > the original sbsa mode of operation and the Marvell mode of > operation. > > > Elad Nachman (3): > dt-bindings: watchdog: add Marvell AC5 watchdog > arm64: dts: ac5: add watchdog nodes > watchdog: sbsa_gwdt: add support for Marvell ac5 > > .../bindings/watchdog/arm,sbsa-gwdt.yaml | 52 +++- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 14 + > arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 8 + > drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++-- > 4 files changed, 298 insertions(+), 23 deletions(-) > > -- > 2.25.1 >
On Thu, Dec 14, 2023 at 05:04:14PM +0200, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Add support for Marvell ac5/x variant of the ARM > sbsa global watchdog. This watchdog deviates from > the standard driver by the following items: > > 1. Registers reside in secure register section. > hence access is only possible via SMC calls to ATF. > > 2. There are couple more registers which reside in > other register areas, which needs to be configured > in order for the watchdog to properly generate > reset through the SOC. > > The new Marvell compatibility string differentiates between > the original sbsa mode of operation and the Marvell mode of > operation. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++++++++++++++++++--- That's more than half the existing driver... > 1 file changed, 226 insertions(+), 21 deletions(-) > > diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c > index 5f23913ce3b4..0bc6f53f0968 100644 > --- a/drivers/watchdog/sbsa_gwdt.c > +++ b/drivers/watchdog/sbsa_gwdt.c > @@ -46,10 +46,13 @@ > #include <linux/mod_devicetable.h> > #include <linux/module.h> > #include <linux/moduleparam.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/uaccess.h> > #include <linux/watchdog.h> > #include <asm/arch_timer.h> > +#include <linux/arm-smccc.h> > > #define DRV_NAME "sbsa-gwdt" > #define WATCHDOG_NAME "SBSA Generic Watchdog" > @@ -75,6 +78,68 @@ > #define SBSA_GWDT_VERSION_MASK 0xF > #define SBSA_GWDT_VERSION_SHIFT 16 > > +/* Marvell AC5/X SMCs, taken from arm trusted firmware */ > +#define SMC_FID_READ_REG 0x80007FFE > +#define SMC_FID_WRITE_REG 0x80007FFD > + > +/* Marvell registers offsets: */ > +#define SBSA_GWDT_MARVELL_CPU_WD_RST_EN_REG 0x30 > +#define SBSA_GWDT_MARVELL_MNG_ID_REG 0x4C > +#define SBSA_GWDT_MARVELL_RST_CTRL_REG 0x0C > + > +#define SBSA_GWDT_MARVELL_ID_MASK GENMASK(19, 12) > +#define SBSA_GWDT_MARVELL_AC5_ID 0xB4000 > +#define SBSA_GWDT_MARVELL_AC5X_ID 0x98000 > +#define SBSA_GWDT_MARVELL_IML_ID 0xA0000 > +#define SBSA_GWDT_MARVELL_IMM_ID 0xA2000 > + > +#define SBSA_GWDT_MARVELL_AC5_RST_UNIT_WD_BIT BIT(6) > +/* The following applies to AC5X, IronMan L and M: */ > +#define SBSA_GWDT_MARVELL_IRONMAN_RST_UNIT_WD_BIT BIT(7) > + > +/* > + * Action to perform after watchdog gets WS1 (watchdog signal 1) interrupt > + * PWD = Private Watchdog, GWD - Global Watchdog, mpp - multi purpose pin > + * > + * 0 = Enable 1 = Disable (Default) > + * > + * BIT 0: CPU 0 reset by PWD 0 > + * BIT 1: CPU 1 reset by PWD 1 > + * BIT 2: CPU 0 reset by GWD > + * BIT 3: CPU 1 reset by GWD > + * BIT 4: PWD 0 sys reset out > + * BIT 5: PWD 1 sys reset out > + * BIT 6: GWD sys reset out > + * BIT 7: Reserved > + * BIT 8: PWD 0 mpp reset out > + * BIT 9: PWD 1 mpp reset out > + * BIT 10: GWD mpp reset out > + * > + */ > +#define SBSA_GWDT_MARVELL_RST_CPU0_BY_PWD0 BIT(0) > +#define SBSA_GWDT_MARVELL_RST_CPU1_BY_PWD1 BIT(1) > +#define SBSA_GWDT_MARVELL_RST_CPU0_BY_GWD BIT(2) > +#define SBSA_GWDT_MARVELL_RST_CPU1_BY_GWD BIT(3) > +#define SBSA_GWDT_MARVELL_RST_SYSRST_BY_PWD0 BIT(4) > +#define SBSA_GWDT_MARVELL_RST_SYSRST_BY_PWD1 BIT(5) > +#define SBSA_GWDT_MARVELL_RST_SYSRST_BY_GWD BIT(6) > +#define SBSA_GWDT_MARVELL_RST_RESERVED BIT(7) > +#define SBSA_GWDT_MARVELL_RST_MPP_BY_PWD0 BIT(8) > +#define SBSA_GWDT_MARVELL_RST_MPP_BY_PWD1 BIT(9) > +#define SBSA_GWDT_MARVELL_RST_MPP_BY_GWD BIT(10) > + > +/** > + * struct sbsa_gwdt_regs_ops - ops for register read/write, depending on SOC > + * @reg_read: register read ops function > + * @read_write: register write ops function > + */ > +struct sbsa_gwdt_regs_ops { > + u32 (*reg_read32)(void __iomem *ptr); > + __u64 (*reg_read64)(void __iomem *ptr); > + void (*reg_write32)(u32 val, void __iomem *ptr); > + void (*reg_write64)(__u64 val, void __iomem *ptr); > +}; > + > /** > * struct sbsa_gwdt - Internal representation of the SBSA GWDT > * @wdd: kernel watchdog_device structure > @@ -89,6 +154,7 @@ struct sbsa_gwdt { > int version; > void __iomem *refresh_base; > void __iomem *control_base; > + const struct sbsa_gwdt_regs_ops *soc_reg_ops; > }; > > #define DEFAULT_TIMEOUT 10 /* seconds */ > @@ -116,6 +182,91 @@ MODULE_PARM_DESC(nowayout, > "Watchdog cannot be stopped once started (default=" > __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); > > +/* > + * By default, have the Global watchdog cause System Reset: > + */ > +static unsigned int reset = 0xFFFFFFFF ^ SBSA_GWDT_MARVELL_RST_SYSRST_BY_GWD; > +module_param(reset, uint, 0); > +MODULE_PARM_DESC(reset, "Action to perform after watchdog gets WS1 interrupt"); > + > +/* > + * Marvell AC5/X use SMC, while others use direct register access > + */ > +static u32 sbsa_gwdt_smc_readl(void __iomem *addr) > +{ > + struct arm_smccc_res smc_res; > + > + arm_smccc_smc(SMC_FID_READ_REG, (unsigned long)addr, > + 0, 0, 0, 0, 0, 0, &smc_res); > + return (u32)smc_res.a0; > +} > + > +static void sbsa_gwdt_smc_writel(u32 val, void __iomem *addr) > +{ > + struct arm_smccc_res smc_res; > + > + arm_smccc_smc(SMC_FID_WRITE_REG, (unsigned long)addr, > + (unsigned long)val, 0, 0, 0, 0, 0, &smc_res); > +} > + > +static inline u64 sbsa_gwdt_lo_hi_smc_readq(void __iomem *addr) > +{ > + u32 low, high; > + > + low = sbsa_gwdt_smc_readl(addr); > + high = sbsa_gwdt_smc_readl(addr + 4); > + /* read twice, as a workaround to HW limitation */ > + low = sbsa_gwdt_smc_readl(addr); > + > + return low + ((u64)high << 32); > +} > + > +static inline void sbsa_gwdt_lo_hi_smc_writeq(__u64 val, void __iomem *addr) > +{ > + u32 low, high; > + > + low = val & 0xffffffff; > + high = val >> 32; > + sbsa_gwdt_smc_writel(low, addr); > + sbsa_gwdt_smc_writel(high, addr + 4); > + /* write twice, as a workaround to HW limitation */ > + sbsa_gwdt_smc_writel(low, addr); > +} > + > +static u32 sbsa_gwdt_direct_reg_readl(void __iomem *addr) > +{ > + return readl(addr); > +} > + > +static void sbsa_gwdt_direct_reg_writel(u32 val, void __iomem *addr) > +{ > + writel(val, addr); > +} > + > +static inline u64 sbsa_gwdt_lo_hi_direct_readq(void __iomem *addr) > +{ > + return lo_hi_readq(addr); > +} > + > +static inline void sbsa_gwdt_lo_hi_direct_writeq(__u64 val, void __iomem *addr) > +{ > + lo_hi_writeq(val, addr); > +} > + > +static const struct sbsa_gwdt_regs_ops smc_reg_ops = { > + .reg_read32 = sbsa_gwdt_smc_readl, > + .reg_read64 = sbsa_gwdt_lo_hi_smc_readq, > + .reg_write32 = sbsa_gwdt_smc_writel, > + .reg_write64 = sbsa_gwdt_lo_hi_smc_writeq > +}; > + > +static const struct sbsa_gwdt_regs_ops direct_reg_ops = { > + .reg_read32 = sbsa_gwdt_direct_reg_readl, > + .reg_read64 = sbsa_gwdt_lo_hi_direct_readq, > + .reg_write32 = sbsa_gwdt_direct_reg_writel, > + .reg_write64 = sbsa_gwdt_lo_hi_smc_writeq > +}; The watchdog_ops are already practically not much more than a register read or write. Do we really need 2 levels of ops here? > + > /* > * Arm Base System Architecture 1.0 introduces watchdog v1 which > * increases the length watchdog offset register to 48 bits. > @@ -127,17 +278,17 @@ MODULE_PARM_DESC(nowayout, > static u64 sbsa_gwdt_reg_read(struct sbsa_gwdt *gwdt) > { > if (gwdt->version == 0) > - return readl(gwdt->control_base + SBSA_GWDT_WOR); > + return gwdt->soc_reg_ops->reg_read32(gwdt->control_base + SBSA_GWDT_WOR); > else > - return lo_hi_readq(gwdt->control_base + SBSA_GWDT_WOR); > + return gwdt->soc_reg_ops->reg_read64(gwdt->control_base + SBSA_GWDT_WOR); > } Here we already have a different way to abstract register accesses. Probably should have something that works for all 3 cases... Rob
On 12/15/23 10:01, Rob Herring wrote: > On Thu, Dec 14, 2023 at 05:04:14PM +0200, Elad Nachman wrote: >> From: Elad Nachman <enachman@marvell.com> >> >> Add support for Marvell ac5/x variant of the ARM >> sbsa global watchdog. This watchdog deviates from >> the standard driver by the following items: >> >> 1. Registers reside in secure register section. >> hence access is only possible via SMC calls to ATF. >> >> 2. There are couple more registers which reside in >> other register areas, which needs to be configured >> in order for the watchdog to properly generate >> reset through the SOC. >> >> The new Marvell compatibility string differentiates between >> the original sbsa mode of operation and the Marvell mode of >> operation. >> >> Signed-off-by: Elad Nachman <enachman@marvell.com> >> --- >> drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++++++++++++++++++--- > > That's more than half the existing driver... > ... which makes me really unhappy and wonder if it is appropriate to hack up the existing driver that much. it doesn't look like Marvell ac5/x really implements SBSA. Given the large number of device specific deviations, a separate driver may be more appropriate. Guenter
On Thu, Dec 14, 2023 at 9:05 AM Elad Nachman <enachman@marvell.com> wrote: > > From: Elad Nachman <enachman@marvell.com> > > Add support for Marvell ac5/x variant of the ARM > sbsa global watchdog. This watchdog deviates from > the standard driver by the following items: > > 1. Registers reside in secure register section. > hence access is only possible via SMC calls to ATF. > > 2. There are couple more registers which reside in > other register areas, which needs to be configured > in order for the watchdog to properly generate > reset through the SOC. > > The new Marvell compatibility string differentiates between > the original sbsa mode of operation and the Marvell mode of > operation. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++++++++++++++++++--- > 1 file changed, 226 insertions(+), 21 deletions(-) > > diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c > index 5f23913ce3b4..0bc6f53f0968 100644 > --- a/drivers/watchdog/sbsa_gwdt.c > +++ b/drivers/watchdog/sbsa_gwdt.c > @@ -46,10 +46,13 @@ > #include <linux/mod_devicetable.h> > #include <linux/module.h> > #include <linux/moduleparam.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/uaccess.h> > #include <linux/watchdog.h> > #include <asm/arch_timer.h> > +#include <linux/arm-smccc.h> > > #define DRV_NAME "sbsa-gwdt" > #define WATCHDOG_NAME "SBSA Generic Watchdog" > @@ -75,6 +78,68 @@ > #define SBSA_GWDT_VERSION_MASK 0xF > #define SBSA_GWDT_VERSION_SHIFT 16 > > +/* Marvell AC5/X SMCs, taken from arm trusted firmware */ > +#define SMC_FID_READ_REG 0x80007FFE > +#define SMC_FID_WRITE_REG 0x80007FFD One more thing, these IDs are part of the Arm arch range and can't be used. You should be using the SIP range AIUI. Perhaps you should look at arm_smc_wdt.c and make that work on your system. Despite the name, my understanding is it is a ChromeOS defined watchdog, not an Arm (Ltd) one. Rob
From: Elad Nachman <enachman@marvell.com> Add support for Marvell ac5/x variant of the ARM sbsa global watchdog. This watchdog deviates from the standard driver by the following items: 1. Registers reside in secure register section. hence access is only possible via SMC calls to ATF. 2. There are couple more registers which reside in other register areas, which needs to be configured in order for the watchdog to properly generate reset through the SOC. The new Marvell compatibility string differentiates between the original sbsa mode of operation and the Marvell mode of operation. Elad Nachman (3): dt-bindings: watchdog: add Marvell AC5 watchdog arm64: dts: ac5: add watchdog nodes watchdog: sbsa_gwdt: add support for Marvell ac5 .../bindings/watchdog/arm,sbsa-gwdt.yaml | 52 +++- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 14 + arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 8 + drivers/watchdog/sbsa_gwdt.c | 247 ++++++++++++++++-- 4 files changed, 298 insertions(+), 23 deletions(-)