From patchwork Wed Dec 13 07:02:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1875504 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-24617-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Sqmhh3f7Kz1ySd for ; Wed, 13 Dec 2023 18:05:24 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 42B651C209FC for ; Wed, 13 Dec 2023 07:05:22 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 59FEC15AD7; Wed, 13 Dec 2023 07:05:08 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAEA7D0; Tue, 12 Dec 2023 23:05:02 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD737u4032114; Wed, 13 Dec 2023 15:03:07 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:03:06 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 00/16] Support Andes PMU extension Date: Wed, 13 Dec 2023 15:02:45 +0800 Message-ID: <20231213070301.1684751-1-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BD737u4032114 Hi All, This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf. To use FDT-based probing for hardware support of the PMU extensions, we first convert T-Head's PMU to CPU feature alternative, and add Andes PMU alternatives. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable/pending registers (slie/slip), while the interrupt cause is (256 + 18). Mainline OpenSBI has supported Andes PMU extension: - https://github.com/riscv-software-src/opensbi/tree/master Linux patches (based on v6.7-rc5) can be found on Andes Technology GitHub - https://github.com/andestech/linux/commits/andes-pmu-support-v5 The PMU device tree node used on AX45MP: - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3 Locus Wei-Han Chen (1): riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin (15): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Allow large non-standard interrupt number irqchip/riscv-intc: Introduce Andes hart-level interrupt controller dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC perf: RISC-V: Eliminate redundant interrupt enable/disable operations RISC-V: Move T-Head PMU to CPU feature alternative framework perf: RISC-V: Introduce Andes PMU for perf event sampling dt-bindings: riscv: Add T-Head PMU extension description dt-bindings: riscv: Add Andes PMU extension description riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s riscv: dts: sophgo: Add T-Head PMU extension for cv1800b riscv: dts: sophgo: Add T-Head PMU extension for sg2042 riscv: dts: thead: Add T-Head PMU extension for th1520 riscv: dts: renesas: Add Andes PMU extension for r9a07g043f .../devicetree/bindings/riscv/cpus.yaml | 6 +- .../devicetree/bindings/riscv/extensions.yaml | 13 ++ arch/riscv/Kconfig.errata | 13 -- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 +++++++++--------- arch/riscv/boot/dts/thead/th1520.dtsi | 8 +- arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/errata/thead/errata.c | 19 --- arch/riscv/include/asm/errata_list.h | 19 +-- arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 2 + drivers/irqchip/irq-riscv-intc.c | 63 +++++++-- drivers/perf/Kconfig | 27 ++++ drivers/perf/riscv_pmu_sbi.c | 47 +++++-- include/linux/soc/andes/irq.h | 17 +++ .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 +++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 24 files changed, 565 insertions(+), 151 deletions(-) create mode 100644 include/linux/soc/andes/irq.h create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json Acked-by: Conor Dooley Acked-by: Conor Dooley Acked-by: Conor Dooley Acked-by: Conor Dooley Reviewed-by: Conor Dooley