| Message ID | 20231211162331.435900-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On Mon, Dec 11, 2023 at 10:24 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: André Draszik <andre.draszik@linaro.org> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-gs101.c | 2512 +++++++++++++++++++++++++++++++ > 2 files changed, 2513 insertions(+) > create mode 100644 drivers/clk/samsung/clk-gs101.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index ebbeacabe88f..3056944a5a54 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > new file mode 100644 > index 000000000000..05361fce3c6f > --- /dev/null > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -0,0 +1,2512 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin <peter.griffin@linaro.org> > + * > + * Common Clock Framework support for GS101. > + */ > + > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_device.h> You probably don't need this header. Please check. > +#include <linux/platform_device.h>
Hi Rob, Thanks for your review. On Mon, 11 Dec 2023 at 16:43, Rob Herring <robh+dt@kernel.org> wrote: > > On Mon, Dec 11, 2023 at 10:24 AM Peter Griffin <peter.griffin@linaro.org> wrote: > > > > cmu_top is the top level clock management unit which contains PLLs, muxes, > > dividers and gates that feed the other clock management units. > > > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > > APM module. > > > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Reviewed-by: André Draszik <andre.draszik@linaro.org> > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > > Tested-by: Will McVicker <willmcvicker@google.com> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > drivers/clk/samsung/Makefile | 1 + > > drivers/clk/samsung/clk-gs101.c | 2512 +++++++++++++++++++++++++++++++ > > 2 files changed, 2513 insertions(+) > > create mode 100644 drivers/clk/samsung/clk-gs101.c > > > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > > index ebbeacabe88f..3056944a5a54 100644 > > --- a/drivers/clk/samsung/Makefile > > +++ b/drivers/clk/samsung/Makefile > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > > new file mode 100644 > > index 000000000000..05361fce3c6f > > --- /dev/null > > +++ b/drivers/clk/samsung/clk-gs101.c > > @@ -0,0 +1,2512 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Copyright (C) 2023 Linaro Ltd. > > + * Author: Peter Griffin <peter.griffin@linaro.org> > > + * > > + * Common Clock Framework support for GS101. > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/clk-provider.h> > > +#include <linux/of.h> > > +#include <linux/of_device.h> > > You probably don't need this header. Please check. > > > +#include <linux/platform_device.h> You are correct, this header isn't required. If a new series is required I will remove it. Whilst you're here I'd like to draw your attention to [PATCH 2/16] where I've removed your reviewed-by tag in v7 because I added the ect node documentation in google.yaml. The empty ect node is required to be present by the bootloader or the device will boot loop. Can you re-review that patch? The alternative is to remove the empty ect node, and the binding documentation for it and add your Reviewed-by tag back again. But then an upstream kernel won't boot 'out the box' on a pixel 6 which seems less than ideal default behaviour. regards, Peter.
On Mon, Dec 11, 2023 at 5:24 PM Peter Griffin <peter.griffin@linaro.org> wrote: > Add support for the pin-controller found on the gs101 SoC used in > Pixel 6 phones. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Looks good to me. Acked-by: Linus Walleij <linus.walleij@linaro.org> I expect Krzysztof to merge this when he feels it is ready and send to me by pull request. Yours, Linus Walleij
On Mon, 11 Dec 2023 16:23:24 +0000, Peter Griffin wrote: > Add support for the pin-controller found on the gs101 SoC used in > Pixel 6 phones. > > Applied, thanks! [09/16] pinctrl: samsung: Add gs101 SoC pinctrl configuration https://git.kernel.org/pinctrl/samsung/c/4a8be01a1a7a030ae7b6138602d2e060cf7a0946 Best regards,
On 11/12/2023 20:46, Peter Griffin wrote: >>> +#include <linux/platform_device.h> > > You are correct, this header isn't required. If a new series is > required I will remove it. I dropped it while applying. > > Whilst you're here I'd like to draw your attention to [PATCH 2/16] > where I've removed your reviewed-by tag in v7 because I added the ect > node documentation in google.yaml. The empty ect node is required to > be present by the bootloader or the device will boot loop. Can you > re-review that patch? > > The alternative is to remove the empty ect node, and the binding > documentation for it and add your Reviewed-by tag back again. But then > an upstream kernel won't boot 'out the box' on a pixel 6 which seems > less than ideal default behaviour. Best regards, Krzysztof
On Mon, 11 Dec 2023 16:23:22 +0000, Peter Griffin wrote: > These plls are found in the Tensor gs101 SoC found in the Pixel 6. > > pll0516x: Integer PLL with high frequency > pll0517x: Integer PLL with middle frequency > pll0518x: Integer PLL with low frequency > > PLL0516x > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) > > [...] Applied, thanks! [07/16] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} https://git.kernel.org/krzk/linux/c/13ff3bdafdd569e62e59330de18aae25ec15c97b Best regards,
On Mon, 11 Dec 2023 16:23:23 +0000, Peter Griffin wrote: > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > > [...] Applied, thanks! Dropped the header, pointed out by Rob. [08/16] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support https://git.kernel.org/krzk/linux/c/2c597bb7d66a55f2af2fff9bf4629dd07b3b9a1e Best regards,
On Mon, 11 Dec 2023 16:23:28 +0000, Peter Griffin wrote: > Add serial driver data for Google Tensor gs101 SoC and a common > fifoszdt_serial_drv_data that can be used by platforms that specify the > samsung,uart-fifosize DT property. > > A corresponding dt-bindings patch updates the yaml to ensure > samsung,uart-fifosize is a required property. > > [...] Applied, thanks! [13/16] tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data https://git.kernel.org/krzk/linux/c/c95f5b21a0eaa4a2701c28e2b209f9a7e09cd4f0 Best regards,
On Tue, 12 Dec 2023 at 19:38, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 11/12/2023 20:46, Peter Griffin wrote: > >>> +#include <linux/platform_device.h> > > > > You are correct, this header isn't required. If a new series is > > required I will remove it. > > I dropped it while applying. Thanks Krzysztof :)
On 12/11/23 08:23, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > Similar to Exynos850 it has two watchdog instances, one for > each cluster and has some control bits in PMU registers. > > gs101 also has the dbgack_mask bit in wtcon register, so > we also enable QUIRK_HAS_DBGACK_BIT. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/s3c2410_wdt.c | 49 ++++++++++++++++++++++++++++++---- > 1 file changed, 44 insertions(+), 5 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index b7a03668f743..c3046610ab5d 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -69,6 +69,13 @@ > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > > +#define GS_CLUSTER0_NONCPU_OUT 0x1220 > +#define GS_CLUSTER1_NONCPU_OUT 0x1420 > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 > +#define GS_RST_STAT_REG_OFFSET 0x3B44 > + > /** > * DOC: Quirk flags for different Samsung watchdog IP-cores > * > @@ -270,7 +277,35 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, > }; > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 0, > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > + .cnt_en_bit = 8, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | > + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | > + QUIRK_HAS_DBGACK_BIT, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 1, > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > + .cnt_en_bit = 7, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | > + QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG | > + QUIRK_HAS_DBGACK_BIT, > +}; > + > static const struct of_device_id s3c2410_wdt_match[] = { > + { .compatible = "google,gs101-wdt", > + .data = &drv_data_gs101_cl0 }, > { .compatible = "samsung,s3c2410-wdt", > .data = &drv_data_s3c2410 }, > { .compatible = "samsung,s3c6410-wdt", > @@ -605,9 +640,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > } > > #ifdef CONFIG_OF > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ > + /* Choose Exynos9 SoC family driver data w.r.t. cluster index */ > if (variant == &drv_data_exynos850_cl0 || > - variant == &drv_data_exynosautov9_cl0) { > + variant == &drv_data_exynosautov9_cl0 || > + variant == &drv_data_gs101_cl0) { > u32 index; > int err; > > @@ -620,9 +656,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) > case 0: > break; > case 1: > - variant = (variant == &drv_data_exynos850_cl0) ? > - &drv_data_exynos850_cl1 : > - &drv_data_exynosautov9_cl1; > + if (variant == &drv_data_exynos850_cl0) > + variant = &drv_data_exynos850_cl1; > + else if (variant == &drv_data_exynosautov9_cl0) > + variant = &drv_data_exynosautov9_cl1; > + else if (variant == &drv_data_gs101_cl0) > + variant = &drv_data_gs101_cl1; > break; > default: > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
Hi Peter > -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:53 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 09/16] pinctrl: samsung: Add gs101 SoC pinctrl > configuration > > Add support for the pin-controller found on the gs101 SoC used in Pixel 6 > phones. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > --- > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > 3 files changed, 143 insertions(+) > [snip] > > -- > 2.43.0.472.g3155946c3a-goog
Hi Peter > -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:53 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 10/16] watchdog: s3c2410_wdt: Add support for WTCON > register DBGACK_MASK bit > > The WDT uses the CPU core signal DBGACK to determine whether the SoC is > running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid > checkpatch --strict warnings. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 28 +++++++++++++++++++++++++--- > 1 file changed, 25 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c > b/drivers/watchdog/s3c2410_wdt.c index 0b4bd883ff28..7ecb762a371d > 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -9,6 +9,7 @@ > * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> > */ > > +#include <linux/bits.h> > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/types.h> > @@ -34,9 +35,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN BIT(0) > +#define S3C2410_WTCON_INTEN BIT(2) > +#define S3C2410_WTCON_ENABLE BIT(5) > +#define S3C2410_WTCON_DBGACK_MASK BIT(16) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +102,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. > CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make > watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. > Setting > + the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in > debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) Probably these above defines might also give checkpatch --strict warnings, so you can change to use BIT macro here as well. > +#define QUIRK_HAS_DBGACK_BIT BIT(5) > > /* These quirks require that we have a PMU register map */ #define > QUIRKS_HAVE_PMUREG \ @@ -375,6 +382,19 @@ static int > s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +/* Disable watchdog outputs if CPU is in debug mode */ static void > +s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) { > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); } > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); @@ -700,6 > +720,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. > Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the > watchdog. > -- > 2.43.0.472.g3155946c3a-goog
> -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:53 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 11/16] watchdog: s3c2410_wdt: Update QUIRK macros to > use BIT macro > > Update the remaining QUIRK macros to use the BIT macro. > Ah! I see you have change use BIT here, so you can squash this patch to patch 10/16 or Move BIT change from patch 10/16 to this patch. Either way is fine. > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c > b/drivers/watchdog/s3c2410_wdt.c index 7ecb762a371d..b7a03668f743 > 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -107,11 +107,11 @@ > * DBGACK_MASK bit disables the watchdog outputs when the SoC is in > debug mode. > * Debug mode is determined by the DBGACK CPU signal. > */ > -#define QUIRK_HAS_WTCLRINT_REG (1 << 0) > -#define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > -#define QUIRK_HAS_PMU_RST_STAT (1 << 2) > -#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > -#define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_WTCLRINT_REG BIT(0) > +#define QUIRK_HAS_PMU_MASK_RESET BIT(1) > +#define QUIRK_HAS_PMU_RST_STAT BIT(2) > +#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) > +#define QUIRK_HAS_PMU_CNT_EN BIT(4) > #define QUIRK_HAS_DBGACK_BIT BIT(5) > > /* These quirks require that we have a PMU register map */ > -- > 2.43.0.472.g3155946c3a-goog
> -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:53 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 12/16] watchdog: s3c2410_wdt: Add support for Google > gs101 SoC > > This patch adds the compatibles and drvdata for the Google > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > Similar to Exynos850 it has two watchdog instances, one for each cluster and > has some control bits in PMU registers. > > gs101 also has the dbgack_mask bit in wtcon register, so we also enable > QUIRK_HAS_DBGACK_BIT. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/watchdog/s3c2410_wdt.c | 49 > ++++++++++++++++++++++++++++++---- > 1 file changed, 44 insertions(+), 5 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c > b/drivers/watchdog/s3c2410_wdt.c index b7a03668f743..c3046610ab5d > 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -69,6 +69,13 @@ > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > > [snip] > static const struct of_device_id s3c2410_wdt_match[] = { > + { .compatible = "google,gs101-wdt", > + .data = &drv_data_gs101_cl0 }, > { .compatible = "samsung,s3c2410-wdt", > .data = &drv_data_s3c2410 }, > { .compatible = "samsung,s3c6410-wdt", @@ -605,9 +640,10 @@ > s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct > s3c2410_wdt *wdt) > } > > #ifdef CONFIG_OF > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index > */ > + /* Choose Exynos9 SoC family driver data w.r.t. cluster index */ Exynos9 introduction is out of context here, so you can leave it as original comment, it is not adding anything here. > if (variant == &drv_data_exynos850_cl0 || > - variant == &drv_data_exynosautov9_cl0) { > + variant == &drv_data_exynosautov9_cl0 || > + variant == &drv_data_gs101_cl0) { > u32 index; [snip] > -- > 2.43.0.472.g3155946c3a-goog
> -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:53 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 13/16] tty: serial: samsung: Add gs101 compatible and > common fifoszdt_serial_drv_data > > Add serial driver data for Google Tensor gs101 SoC and a common > fifoszdt_serial_drv_data that can be used by platforms that specify the > samsung,uart-fifosize DT property. > > A corresponding dt-bindings patch updates the yaml to ensure > samsung,uart-fifosize is a required property. > > Tested-by: Will McVicker <willmcvicker@google.com> > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > drivers/tty/serial/samsung_tty.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/tty/serial/samsung_tty.c > b/drivers/tty/serial/samsung_tty.c > index 1b0c2b467a30..71d17d804fda 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -2490,14 +2490,25 @@ static const struct s3c24xx_serial_drv_data > exynos850_serial_drv_data = { > .fifosize = { 256, 64, 64, 64 }, > }; > > +/* > + * Common drv_data struct for platforms that specify > +samsung,uart-fifosize in > + * device tree. > + */ > +static const struct s3c24xx_serial_drv_data > exynos_fifoszdt_serial_drv_data = { > + EXYNOS_COMMON_SERIAL_DRV_DATA(), > + .fifosize = { 0 }, > +}; [snip] > MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); > -- > 2.43.0.472.g3155946c3a-goog
> -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:54 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 15/16] arm64: dts: exynos: google: Add initial Oriole/pixel > 6 board support > > Add initial board support for the Pixel 6 phone code named Oriole. This has > been tested with a minimal busybox initramfs and boots to a shell. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > arch/arm64/boot/dts/exynos/Makefile | 2 + > arch/arm64/boot/dts/exynos/google/Makefile | 4 + > .../boot/dts/exynos/google/gs101-oriole.dts | 105 ++++++++++++++++++ > 3 files changed, 111 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile > create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts > > diff --git a/arch/arm64/boot/dts/exynos/Makefile > b/arch/arm64/boot/dts/exynos/Makefile > index 6e4ba69268e5..44c24a8ad9e1 100644 > --- a/arch/arm64/boot/dts/exynos/Makefile > +++ b/arch/arm64/boot/dts/exynos/Makefile > @@ -1,4 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += google > + > dtb-$(CONFIG_ARCH_EXYNOS) += \ > exynos5433-tm2.dtb \ > exynos5433-tm2e.dtb \ > diff --git a/arch/arm64/boot/dts/exynos/google/Makefile > b/arch/arm64/boot/dts/exynos/google/Makefile > new file mode 100644 > index 000000000000..0a6d5e1fe4ee > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/Makefile > @@ -0,0 +1,4 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +dtb-$(CONFIG_ARCH_EXYNOS) += \ > + gs101-oriole.dtb \ > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts > b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts > new file mode 100644 > index 000000000000..4a71f752200d > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts > @@ -0,0 +1,105 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Oriole Device Tree > + * > + * Copyright 2021-2023 Google LLC > + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include "gs101-pinctrl.h" > +#include "gs101.dtsi" > + > +/ { > + model = "Oriole"; > + compatible = "google,gs101-oriole", "google,gs101"; > + > + aliases { > + serial0 = &serial_0; > + }; > + > + chosen { > + /* Bootloader expects bootargs specified otherwise it > crashes */ > + bootargs = ""; > + stdout-path = &serial_0; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&key_voldown>, <&key_volup>, > <&key_power>; > + > + button-vol-down { > + label = "KEY_VOLUMEDOWN"; > + linux,code = <KEY_VOLUMEDOWN>; > + gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; > + wakeup-source; > + }; > + > + button-vol-up { > + label = "KEY_VOLUMEUP"; > + linux,code = <KEY_VOLUMEUP>; > + gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; > + wakeup-source; > + }; > + > + button-power { > + label = "KEY_POWER"; > + linux,code = <KEY_POWER>; > + gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; > + wakeup-source; > + }; > + }; > +}; > + > +&ext_24_5m { > + clock-frequency = <24576000>; > +}; > + > +&ext_200m { > + clock-frequency = <200000000>; > +}; > + > +&pinctrl_far_alive { > + key_voldown: key-voldown-pins { > + samsung,pins = "gpa7-3"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > + > + key_volup: key-volup-pins { > + samsung,pins = "gpa8-1"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&pinctrl_gpio_alive { > + key_power: key-power-pins { > + samsung,pins = "gpa10-1"; > + samsung,pin-function = <GS101_PIN_FUNC_EINT>; > + samsung,pin-pud = <GS101_PIN_PULL_NONE>; > + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; > + }; > +}; > + > +&serial_0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_bus>; > + status = "okay"; > +}; > + > +&usi_uart { > + samsung,clkreq-on; /* needed for UART mode */ > + status = "okay"; > +}; > + > +&watchdog_cl0 { > + timeout-sec = <30>; > + status = "okay"; > +}; > -- > 2.43.0.472.g3155946c3a-goog
> -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Monday, December 11, 2023 9:54 PM > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > will@kernel.org; arnd@arndb.de; olof@lixom.net; > gregkh@linuxfoundation.org; jirislaby@kernel.org; > cw00.choi@samsung.com; alim.akhtar@samsung.com > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > andre.draszik@linaro.org; semen.protsenko@linaro.org; > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > team@android.com; linux-serial@vger.kernel.org > Subject: [PATCH v7 16/16] MAINTAINERS: add entry for Google Tensor SoC > > Add maintainers entry for the Google tensor SoC based platforms. > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > MAINTAINERS | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 98f7dd0499f1..b731d6b9876a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -8990,6 +8990,16 @@ S: Maintained > T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrome- > platform/linux.git > F: drivers/firmware/google/ > > +GOOGLE TENSOR SoC SUPPORT > +M: Peter Griffin <peter.griffin@linaro.org> > +L: linux-arm-kernel@lists.infradead.org (moderated for non- > subscribers) > +L: linux-samsung-soc@vger.kernel.org > +S: Maintained > +F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > +F: arch/arm64/boot/dts/exynos/google/ > +F: drivers/clk/samsung/clk-gs101.c > +F: include/dt-bindings/clock/google,clk-gs101.h > + > GPD POCKET FAN DRIVER > M: Hans de Goede <hdegoede@redhat.com> > L: platform-driver-x86@vger.kernel.org > -- > 2.43.0.472.g3155946c3a-goog
Hi Alim, Thanks for your reviews. On Wed, 13 Dec 2023 at 16:34, Alim Akhtar <alim.akhtar@samsung.com> wrote: > > > > > -----Original Message----- > > From: Peter Griffin <peter.griffin@linaro.org> > > Sent: Monday, December 11, 2023 9:53 PM > > To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > > mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; > > tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; > > wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; > > will@kernel.org; arnd@arndb.de; olof@lixom.net; > > gregkh@linuxfoundation.org; jirislaby@kernel.org; > > cw00.choi@samsung.com; alim.akhtar@samsung.com > > Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; > > andre.draszik@linaro.org; semen.protsenko@linaro.org; > > saravanak@google.com; willmcvicker@google.com; soc@kernel.org; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > > samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > > gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- > > team@android.com; linux-serial@vger.kernel.org > > Subject: [PATCH v7 11/16] watchdog: s3c2410_wdt: Update QUIRK macros to > > use BIT macro > > > > Update the remaining QUIRK macros to use the BIT macro. > > > Ah! I see you have change use BIT here, so you can squash this patch to > patch 10/16 or > Move BIT change from patch 10/16 to this patch. Either way is fine. I actually kept them separate deliberately to avoid conflating adding of the DBGACK quirk with cleanup of the driver to use BIT macro. As such one patch adds the QUIRK and only updates the macros that were touched by that patch (to avoid the --strict warnings), and the second patch cleans up the rest of the macros to use BIT macro for consistency. regards, Peter
On 13/12/2023 17:42, Alim Akhtar wrote: >> static const struct of_device_id s3c2410_wdt_match[] = { >> + { .compatible = "google,gs101-wdt", >> + .data = &drv_data_gs101_cl0 }, >> { .compatible = "samsung,s3c2410-wdt", >> .data = &drv_data_s3c2410 }, >> { .compatible = "samsung,s3c6410-wdt", @@ -605,9 +640,10 @@ >> s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct >> s3c2410_wdt *wdt) >> } >> >> #ifdef CONFIG_OF >> - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index >> */ >> + /* Choose Exynos9 SoC family driver data w.r.t. cluster index */ > Exynos9 introduction is out of context here, so you can leave it as original > comment, it is not adding anything here. Dropped that hunk and applied. Best regards, Krzysztof
On Mon, 11 Dec 2023 16:23:25 +0000, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid > checkpatch --strict warnings. > > [...] Applied, thanks! [10/16] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit https://git.kernel.org/krzk/linux/c/6584cd34901056bc12e015781e4adf03b44ba485 Best regards,
On Mon, 11 Dec 2023 16:23:26 +0000, Peter Griffin wrote: > Update the remaining QUIRK macros to use the BIT macro. > > Applied, thanks! [11/16] watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro https://git.kernel.org/krzk/linux/c/d429928dde2d7e3e98cbea5f170d089d10a45c39 Best regards,
On Mon, 11 Dec 2023 16:23:27 +0000, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > Similar to Exynos850 it has two watchdog instances, one for > each cluster and has some control bits in PMU registers. > > gs101 also has the dbgack_mask bit in wtcon register, so > we also enable QUIRK_HAS_DBGACK_BIT. > > [...] Applied, thanks! [12/16] watchdog: s3c2410_wdt: Add support for Google gs101 SoC https://git.kernel.org/krzk/linux/c/796bb2d3a16c1e786ed51183162783405b5c8f85 Best regards,
On Mon, 11 Dec 2023 16:23:30 +0000, Peter Griffin wrote: > Add initial board support for the Pixel 6 phone code named Oriole. This > has been tested with a minimal busybox initramfs and boots to a shell. > > Applied, thanks! [15/16] arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support https://git.kernel.org/krzk/linux/c/6a5713fc7853c3998c706cb809c5d9fd1c6acaa5 Best regards,
On Mon, 11 Dec 2023 16:23:31 +0000, Peter Griffin wrote: > Add maintainers entry for the Google tensor SoC based > platforms. > > Applied, thanks! [16/16] MAINTAINERS: add entry for Google Tensor SoC https://git.kernel.org/krzk/linux/c/9d71df3e6eb773f23d6f1f3f8790bae6aba1a088 Best regards,
On 13/12/2023 20:13, Peter Griffin wrote: > Hi Alim, > > Thanks for your reviews. > > On Wed, 13 Dec 2023 at 16:34, Alim Akhtar <alim.akhtar@samsung.com> wrote: >> >> >> >>> -----Original Message----- >>> From: Peter Griffin <peter.griffin@linaro.org> >>> Sent: Monday, December 11, 2023 9:53 PM >>> To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; >>> mturquette@baylibre.com; conor+dt@kernel.org; sboyd@kernel.org; >>> tomasz.figa@gmail.com; s.nawrocki@samsung.com; linus.walleij@linaro.org; >>> wim@linux-watchdog.org; linux@roeck-us.net; catalin.marinas@arm.com; >>> will@kernel.org; arnd@arndb.de; olof@lixom.net; >>> gregkh@linuxfoundation.org; jirislaby@kernel.org; >>> cw00.choi@samsung.com; alim.akhtar@samsung.com >>> Cc: peter.griffin@linaro.org; tudor.ambarus@linaro.org; >>> andre.draszik@linaro.org; semen.protsenko@linaro.org; >>> saravanak@google.com; willmcvicker@google.com; soc@kernel.org; >>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- >>> samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- >>> gpio@vger.kernel.org; linux-watchdog@vger.kernel.org; kernel- >>> team@android.com; linux-serial@vger.kernel.org >>> Subject: [PATCH v7 11/16] watchdog: s3c2410_wdt: Update QUIRK macros to >>> use BIT macro >>> >>> Update the remaining QUIRK macros to use the BIT macro. >>> >> Ah! I see you have change use BIT here, so you can squash this patch to >> patch 10/16 or >> Move BIT change from patch 10/16 to this patch. Either way is fine. > > I actually kept them separate deliberately to avoid conflating adding > of the DBGACK quirk with cleanup of the driver to use BIT macro. > > As such one patch adds the QUIRK and only updates the macros that were > touched by that patch (to avoid the --strict warnings), and the second > patch cleans up the rest of the macros to use BIT macro for > consistency. Yeah, the defines are from existing code, so not really related to GS101 patch. Keeping it as separate cleanup is fine. Best regards, Krzysztof
Hi folks, This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). Thankyou to everyone who has reviewed and tested the previous series. Your time and effort doing so is much appreciated! If any relevant subsystem maintainers can send a acked-by that would be much appreciated. In particular @RobH: Please can you re-review google.yaml as a ect node was added since you gave your previous reviewed-by @Guenter/Wim: If you're happy, can you send an acked-by for Watchdog changes? V7 incorporates the review feedback received so far, and is rebased onto linux-next as per Krzysztof request to incorporate all his dt-binding changes for exynos. I'm really hoping V7 will be the last series, and we can get this series merged this week so it will make it into v6.8 Linux release. v7 fixes up various cosmetic nits in device tree and drivers regarding alphabetical ordering. See below for more verbose details. There is one additional patch to fixup some incorrect numbering and spelling typo in the google,gs101.h. Also the patches which have already been applied have been dropped from the series. As this series spans multiple subsytems the expectation is that Krzysztof will apply the whole series through the Samsung SoC tree. If the relevant subsystem maintainers can give a acked-by or reviewed-by on the relevant patches that would be most appreciated! The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven) phones. Currently DT is added for the gs101 SoC and Oriole. As you can see from the patches the SoC is based on a Samsung Exynos SoC, and therefore lots of the low level Exynos drivers and bindings can be re-used. The support added in this series consists of: * cpus * pinctrl * CCF implementation of cmu_top, cmu_misc & cmu_apm * watchdog * USI uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts Note: Booting without a dtbo works with some versions of the bootloader but crashes on others. Later versions aren't necessarily better. You can get the bootloader version with `fastboot getvar version-bootloader` Known good bootloader versions are: - - slider-1.3-11000330 - slider-1.2-9152140 Known to crash without dtbo - slider-1.3-10780582 kind regards, Peter. lore v6: https://lore.kernel.org/all/25533a7f-326f-48d1-a8a6-e5798bdca4b4@linaro.org/T/ lore v5: https://lore.kernel.org/all/20231201160925.3136868-1-peter.griffin@linaro.org/T/ lore v4: https://lore.kernel.org/linux-arm-kernel/20231120212037.911774-1-peter.griffin@linaro.org/T/ pw v3: https://patchwork.kernel.org/project/linux-samsung-soc/cover/20231011184823.443959-1-peter.griffin@linaro.org/ lore v2: https://lore.kernel.org/all/20231010224928.2296997-1-peter.griffin@linaro.org/ lore v1: https://lore.kernel.org/linux-arm-kernel/20231005155618.700312-1-peter.griffin@linaro.org/ Changes since v6: - Collect up Reviewed-by tags - s3c2410_wdt: alphabetical ordering of compatible (Krzysztof) - pinctrl-samsung: alphabetical ordering of compatible (Krzysztof) - gs101.dtsi: alphabetical node ordering, vendor properties end of node (Krzysztof) - Header guard doesn't match location (Krzysztof) - Fix incorrect numbering and spelling typo in google,gs101 and clk-gs101 (Andre) Changes since v5: - Collect up Reviewed-by and Tested-by tags - clk-gs101: reorder cmu_top parents in register offset order (Peter) - clk-gs101: Review cmu_top and cmu_misc parents, fix a few typos - clk-gs101: Add more name mangling to shorten DT and Linux clock name strings (Sam) - pinctrl: samsung: Drop support for digital/analog selectable filters (Peter) - Fixup cmu_top yaml example and some nitpicks (Sam) - Fixup some spelling nitpicks in google.yaml (Sam) - samsung,pinctrl-wakeup-interrupt: drop second not required google,gs101-wakeup-eint compatible (Krzysztof) - exynos-usi.yaml: add google,gs101-usi to previous enum (Krzysztof) - s3c2410_wdt: move comment, double whitespace, add BIT macro (Sam) Changes since v4: - clk-gs101: order cmu_top by register address, fix incorrect mux widths, add missing mux/div/gates (Andre) - google,gs101.h: add missing space in comment (Andre) - ckl-gs101:google,gs101.h add all remaining gates for cmu_misc and cmu_apm - update pmu dt labels (Krzysztof) - Remove uart16 rts/tx gpio definitions (Krzysztof) - Fixup various dts cosmetic nits (using consts, alignments, names) (Sam/Krzysztof) - Add more specific compatibles for arm cpu's and pmu (Sam) - Use address-cells 1 and ranges property for SoC addresses (Sam) - Encapsulate uart node in USI node (Sam) - Remove earlycon from bootargs - s3c2410_wdt: Reword QUIRK_HAS_DBGACK_BIT docs and add comment (Guenter) - s3c2410_wdt: Reorder DBGACK_MASK functionality first, gs101 SoC second (Sam/Krzysztof) Changes since v3: - Add reviewed-by and tested-by tags - google,gs101-clock.yaml: move Required to before Allof, enum for cmu*top/misc (Krzysztof) - samsung-wdt.yaml: stick to 80chars (Sam) - google.yaml - remove new line - samsung,pinctrl-wakeup-interrupt: sort alphabetically (RobH) - gs101-oriole.dts: update gpio-keys pinctrl-0 phandle for keys (Stephen) - samsung,exynos-sysreg.yaml - Alphabetical order (RobH) - pinctrl-exynos: update/move comments, slight cosmetic changes (Sam) - samsung_tty.c: update to generic drv_data name/macro (Arnd) - samsung_uart.yaml: make samsung,uart-fifosize required for gs101-uart (Arnd) - pinctrl-exynos: Remove eint irqs from alive pin controller node (Peter/Rob) - Fixup kernel test robot unused const variable warnings - clk-gs101: Update to mout_cmu_eh_bus to CLK_CON_MUX_MUX_CLKCMU_EH_BUS (Chanwoo) - clk-gs101: Update g3aa gout/dout/mout names to g3aa_g3aa for consistency (Chanwoo) - Remove .eint_gpio_init() cb on alive, alive_far, gsacore & gsactrl banks (Sam) - s3c2410_wdt: Drop windowed watchdog mode for now (Peter) - s3c2410_wdt: Separate gs101 SoC support from dbgack feature (Sam) - Move dts to arch/arm64/boot/dts/exynos/google directory (Krzysztof) Changes since v2: - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor) - Add missing windowed watchdog code (Guenter) - Fixup UART YAML bindings error (Krzysztof) - gs101.dtsi add missing serial_0 alias (me) - samsung_tty.c: fixup gs101_serial_drv_data so fifosize is obtained from DT Changes since v1: - Remove irq/gs101.h and replace macros with irq numbers globally - exynos-pmu - keep alphabetical order - add cmu_apm to clock bindings documentation - sysreg bindings - remove superfluous `google,gs101-sysreg` - watchdog bindings - Alphanumerical order, update gs201 comment - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order - samsung,pinctrl- add google,gs101-wakeup-eint compatible - clk-pll: fixup typos - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) - clk-gs101: fix alphabetical order - clk-gs101: cmu_apm: fixup typo and missing empty entry - clk-gs101: cmu_misc: remove clocks that were being registerred twice - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter - watchdog: s3c2410_wdt: remove dev_info prints - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix - gs101-oriole.dtso: Remove overlay until board_id is documented properly - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones - gpio-keys: update linux,code to use input-event-code macros - add dedicated gs101-uart compatible Peter Griffin (15): dt-bindings: watchdog: Document Google gs101 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: serial: samsung: Add google-gs101-uart compatible dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro watchdog: s3c2410_wdt: Add support for Google gs101 SoC tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data arm64: dts: exynos: google: Add initial Google gs101 SoC support arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support MAINTAINERS: add entry for Google Tensor SoC Tudor Ambarus (1): dt-bindings: soc: samsung: usi: add google,gs101-usi compatible .../devicetree/bindings/arm/google.yaml | 53 + .../bindings/serial/samsung_uart.yaml | 11 + .../bindings/soc/samsung/exynos-usi.yaml | 1 + .../bindings/watchdog/samsung-wdt.yaml | 8 +- MAINTAINERS | 10 + arch/arm64/boot/dts/exynos/Makefile | 2 + arch/arm64/boot/dts/exynos/google/Makefile | 4 + .../boot/dts/exynos/google/gs101-oriole.dts | 105 + .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1249 ++++++++ .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 473 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2512 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 6 + drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 + drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + drivers/tty/serial/samsung_tty.c | 16 + drivers/watchdog/s3c2410_wdt.c | 87 +- include/dt-bindings/clock/google,gs101.h | 118 +- 21 files changed, 4761 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c