| Message ID | 20231209233106.147416-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 10/12/2023 00:30, Peter Griffin wrote: > Add support for the pin-controller found on the gs101 SoC used in > Pixel 6 phones. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > index 6b58ec84e34b..3834bf953178 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -468,6 +468,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { > .data = &exynos7_wkup_irq_chip }, > { .compatible = "samsung,exynosautov9-wakeup-eint", > .data = &exynos7_wkup_irq_chip }, > + { .compatible = "google,gs101-wakeup-eint", > + .data = &exynos7_wkup_irq_chip }, You don't need it. > { } > }; > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > index 79babbb39ced..b8d549fe38cb 100644 > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { > .data = &exynosautov9_of_data }, > { .compatible = "tesla,fsd-pinctrl", > .data = &fsd_of_data }, > + { .compatible = "google,gs101-pinctrl", > + .data = &gs101_of_data }, Place it somewhere alphabetically. Probably before tesla. Best regards, Krzysztof
On 10/12/2023 00:31, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid > checkpatch --strict warnings. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Guenter, Wim, The watchdog patches are kind of independent, except that bindings has conflicting re-organization which I took via my Samsung SoC tree. If it is fine with you, please provide acks or review and I will take the watchdog changes. Best regards, Krzysztof
On 10/12/2023 00:31, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > Similar to Exynos850 it has two watchdog instances, one for > each cluster and has some control bits in PMU registers. > > + > static const struct of_device_id s3c2410_wdt_match[] = { > { .compatible = "samsung,s3c2410-wdt", > .data = &drv_data_s3c2410 }, > @@ -285,6 +318,8 @@ static const struct of_device_id s3c2410_wdt_match[] = { > .data = &drv_data_exynos850_cl0 }, > { .compatible = "samsung,exynosautov9-wdt", > .data = &drv_data_exynosautov9_cl0 }, > + { .compatible = "google,gs101-wdt", > + .data = &drv_data_gs101_cl0 }, Keep some alphabetical order by compatible, so this should be probably the first entry in the table. Same for s3c2410_wdt_variant structures. > {}, Best regards, Krzysztof
On 10/12/2023 00:30, Peter Griffin wrote: > Hi folks, > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > I started applying few reviewed bindings. We are getting close to end of merging time for SoC. Top-level arm/google.yaml needs ack or re-review from Rob. Best regards, Krzysztof
On 10/12/2023 00:31, Peter Griffin wrote: > Add initial board support for the Pixel 6 phone code named Oriole. This > has been tested with a minimal busybox initramfs and boots to a shell. > > Tested-by: Will McVicker <willmcvicker@google.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > arch/arm64/boot/dts/exynos/Makefile | 2 + ... > +&serial_0 { > + status = "okay"; Keep status the last > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_bus>; > +}; > + > +&usi_uart { > + status = "okay"; Keep status the last > + samsung,clkreq-on; /* needed for UART mode */ > +}; > + > +&watchdog_cl0 { > + timeout-sec = <30>; > + status = "okay"; > +}; Best regards, Krzysztof
On Sat, Dec 9, 2023 at 5:31 PM Peter Griffin <peter.griffin@linaro.org> wrote: > > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> [snip]
On Sat, Dec 9, 2023 at 5:31 PM Peter Griffin <peter.griffin@linaro.org> wrote: > > Update the remaining QUIRK macros to use the BIT macro. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > drivers/watchdog/s3c2410_wdt.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 7ecb762a371d..b7a03668f743 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -107,11 +107,11 @@ > * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > * Debug mode is determined by the DBGACK CPU signal. > */ > -#define QUIRK_HAS_WTCLRINT_REG (1 << 0) > -#define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > -#define QUIRK_HAS_PMU_RST_STAT (1 << 2) > -#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > -#define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_WTCLRINT_REG BIT(0) > +#define QUIRK_HAS_PMU_MASK_RESET BIT(1) > +#define QUIRK_HAS_PMU_RST_STAT BIT(2) > +#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) > +#define QUIRK_HAS_PMU_CNT_EN BIT(4) > #define QUIRK_HAS_DBGACK_BIT BIT(5) > > /* These quirks require that we have a PMU register map */ > -- > 2.43.0.472.g3155946c3a-goog >
On Sun, Dec 10, 2023 at 7:55 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:30, Peter Griffin wrote: > > Add support for the pin-controller found on the gs101 SoC used in > > Pixel 6 phones. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index 6b58ec84e34b..3834bf953178 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -468,6 +468,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { > > .data = &exynos7_wkup_irq_chip }, > > { .compatible = "samsung,exynosautov9-wakeup-eint", > > .data = &exynos7_wkup_irq_chip }, > > + { .compatible = "google,gs101-wakeup-eint", > > + .data = &exynos7_wkup_irq_chip }, > > You don't need it. > > > { } > > }; > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > > index 79babbb39ced..b8d549fe38cb 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > > @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { > > .data = &exynosautov9_of_data }, > > { .compatible = "tesla,fsd-pinctrl", > > .data = &fsd_of_data }, > > + { .compatible = "google,gs101-pinctrl", > > + .data = &gs101_of_data }, > > Place it somewhere alphabetically. Probably before tesla. > Assuming Krzysztof's comments are fixed, you can also add: Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Best regards, > Krzysztof >
On Sat, 2023-12-09 at 23:30 +0000, Peter Griffin wrote: > cmu_top is the top level clock management unit which contains PLLs, muxes, > dividers and gates that feed the other clock management units. > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > APM module. > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Tested-by: Will McVicker <willmcvicker@google.com> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Cheers, André
Hi folks, On Sun, 10 Dec 2023 at 14:24, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:31, Peter Griffin wrote: > > The WDT uses the CPU core signal DBGACK to determine whether the SoC > > is running in debug mode or not. If the DBGACK signal is asserted and > > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > > (disabled). > > > > Presence of the DBGACK_MASK bit is determined by adding a new > > QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid > > checkpatch --strict warnings. > > > > Tested-by: Will McVicker <willmcvicker@google.com> > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > Guenter, Wim, > > The watchdog patches are kind of independent, except that bindings has > conflicting re-organization which I took via my Samsung SoC tree. If it > is fine with you, please provide acks or review and I will take the > watchdog changes. > Just to add, without the Watchdog gs101 changes the system will reset after ~60 seconds, as the bootloader is left running by the bootloader. So it would be nice to get patches in as well if possible. regards, Peter.
Hi Krzysztof, Thanks for the review. On Sun, 10 Dec 2023 at 14:26, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:31, Peter Griffin wrote: > > This patch adds the compatibles and drvdata for the Google > > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. > > > > Similar to Exynos850 it has two watchdog instances, one for > > each cluster and has some control bits in PMU registers. > > > > > > + > > static const struct of_device_id s3c2410_wdt_match[] = { > > { .compatible = "samsung,s3c2410-wdt", > > .data = &drv_data_s3c2410 }, > > @@ -285,6 +318,8 @@ static const struct of_device_id s3c2410_wdt_match[] = { > > .data = &drv_data_exynos850_cl0 }, > > { .compatible = "samsung,exynosautov9-wdt", > > .data = &drv_data_exynosautov9_cl0 }, > > + { .compatible = "google,gs101-wdt", > > + .data = &drv_data_gs101_cl0 }, > > Keep some alphabetical order by compatible, so this should be probably > the first entry in the table. > > Same for s3c2410_wdt_variant structures. Will fix in v7. Thanks, Peter
Hi Krzysztof, Thanks for the review. On Sun, 10 Dec 2023 at 13:56, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:30, Peter Griffin wrote: > > Add support for the pin-controller found on the gs101 SoC used in > > Pixel 6 phones. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index 6b58ec84e34b..3834bf953178 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -468,6 +468,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { > > .data = &exynos7_wkup_irq_chip }, > > { .compatible = "samsung,exynosautov9-wakeup-eint", > > .data = &exynos7_wkup_irq_chip }, > > + { .compatible = "google,gs101-wakeup-eint", > > + .data = &exynos7_wkup_irq_chip }, > > You don't need it. OK will drop > > > { } > > }; > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c > > index 79babbb39ced..b8d549fe38cb 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-samsung.c > > +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c > > @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { > > .data = &exynosautov9_of_data }, > > { .compatible = "tesla,fsd-pinctrl", > > .data = &fsd_of_data }, > > + { .compatible = "google,gs101-pinctrl", > > + .data = &gs101_of_data }, > > Place it somewhere alphabetically. Probably before tesla. Will fix. FYI I was intending to put it at the top ('g' before 's') that also matches the ordering everywhere else e.g. in the YAML docs etc. regards, Peter
Hi Krzysztof, On Sun, 10 Dec 2023 at 14:39, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 10/12/2023 00:31, Peter Griffin wrote: > > Add initial board support for the Pixel 6 phone code named Oriole. This > > has been tested with a minimal busybox initramfs and boots to a shell. > > > > Tested-by: Will McVicker <willmcvicker@google.com> > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > arch/arm64/boot/dts/exynos/Makefile | 2 + > > ... > > > +&serial_0 { > > + status = "okay"; > > Keep status the last Will fix > > > + pinctrl-names = "default"; > > + pinctrl-0 = <&uart0_bus>; > > +}; > > + > > +&usi_uart { > > + status = "okay"; > > Keep status the last Will fix regards, Peter
Hi folks, This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). Thankyou to everyone who has reviewed and tested the previous series. Your time and effort doing so is much appreciated! V6 incorporates the review feedback received so far, and is rebased onto linux-next as per Krzysztof request to incorporate all his dt-binding changes for exynos. I'm really hoping V6 will be the last series, and we can get this series merged this week so it will make it into v6.8 Linux release. The main difference in v6 apart from the various nits and cosmetic changes is I have dropped support for exynos selectable analog/digital filters. I will look to progress that again after this initial series has been merged. I've also done more clock name mangling as per Sam's request to shorten the clock names, and fixed up various issues with clock parenting. As this series spans multiple subsytems the expectation is that Krzysztof will apply the whole series through the Samsung SoC tree. If the relevant subsystem maintainers can give a acked-by or reviewed-by on the relevant patches that would be most appreciated! The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven) phones. Currently DT is added for the gs101 SoC and Oriole. As you can see from the patches the SoC is based on a Samsung Exynos SoC, and therefore lots of the low level Exynos drivers and bindings can be re-used. The support added in this series consists of: * cpus * pinctrl * CCF implementation of cmu_top, cmu_misc & cmu_apm * watchdog * USI uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts Note: Booting without a dtbo works with some versions of the bootloader but crashes on others. Later versions aren't necessarily better. You can get the bootloader version with `fastboot getvar version-bootloader` Known good bootloader versions are: - - slider-1.3-11000330 - slider-1.2-9152140 Known to crash without dtbo - slider-1.3-10780582 kind regards, Peter. lore v5: https://lore.kernel.org/all/20231201160925.3136868-1-peter.griffin@linaro.org/T/ lore v4: https://lore.kernel.org/linux-arm-kernel/20231120212037.911774-1-peter.griffin@linaro.org/T/ pw v3: https://patchwork.kernel.org/project/linux-samsung-soc/cover/20231011184823.443959-1-peter.griffin@linaro.org/ lore v2: https://lore.kernel.org/all/20231010224928.2296997-1-peter.griffin@linaro.org/ lore v1: https://lore.kernel.org/linux-arm-kernel/20231005155618.700312-1-peter.griffin@linaro.org/ Changes since v5: - Collect up Reviewed-by and Tested-by tags - clk-gs101: reorder cmu_top parents in register offset order (Peter) - clk-gs101: Review cmu_top and cmu_misc parents, fix a few typos - clk-gs101: Add more name mangling to shorten DT and Linux clock name strings (Sam) - pinctrl: samsung: Drop support for digital/analog selectable filters (Peter) - Fixup cmu_top yaml example and some nitpicks (Sam) - Fixup some spelling nitpicks in google.yaml (Sam) - samsung,pinctrl-wakeup-interrupt: drop second not required google,gs101-wakeup-eint compatible (Krzysztof) - exynos-usi.yaml: add google,gs101-usi to previous enum (Krzysztof) - s3c2410_wdt: move comment, double whitespace, add BIT macro (Sam) Changes since v4: - clk-gs101: order cmu_top by register address, fix incorrect mux widths, add missing mux/div/gates (Andre) - google,gs101.h: add missing space in comment (Andre) - ckl-gs101:google,gs101.h add all remaining gates for cmu_misc and cmu_apm - update pmu dt labels (Krzysztof) - Remove uart16 rts/tx gpio definitions (Krzysztof) - Fixup various dts cosmetic nits (using consts, alignments, names) (Sam/Krzysztof) - Add more specific compatibles for arm cpu's and pmu (Sam) - Use address-cells 1 and ranges property for SoC addresses (Sam) - Encapsulate uart node in USI node (Sam) - Remove earlycon from bootargs - s3c2410_wdt: Reword QUIRK_HAS_DBGACK_BIT docs and add comment (Guenter) - s3c2410_wdt: Reorder DBGACK_MASK functionality first, gs101 SoC second (Sam/Krzysztof) Changes since v3: - Add reviewed-by and tested-by tags - google,gs101-clock.yaml: move Required to before Allof, enum for cmu*top/misc (Krzysztof) - samsung-wdt.yaml: stick to 80chars (Sam) - google.yaml - remove new line - samsung,pinctrl-wakeup-interrupt: sort alphabetically (RobH) - gs101-oriole.dts: update gpio-keys pinctrl-0 phandle for keys (Stephen) - samsung,exynos-sysreg.yaml - Alphabetical order (RobH) - pinctrl-exynos: update/move comments, slight cosmetic changes (Sam) - samsung_tty.c: update to generic drv_data name/macro (Arnd) - samsung_uart.yaml: make samsung,uart-fifosize required for gs101-uart (Arnd) - pinctrl-exynos: Remove eint irqs from alive pin controller node (Peter/Rob) - Fixup kernel test robot unused const variable warnings - clk-gs101: Update to mout_cmu_eh_bus to CLK_CON_MUX_MUX_CLKCMU_EH_BUS (Chanwoo) - clk-gs101: Update g3aa gout/dout/mout names to g3aa_g3aa for consistency (Chanwoo) - Remove .eint_gpio_init() cb on alive, alive_far, gsacore & gsactrl banks (Sam) - s3c2410_wdt: Drop windowed watchdog mode for now (Peter) - s3c2410_wdt: Separate gs101 SoC support from dbgack feature (Sam) - Move dts to arch/arm64/boot/dts/exynos/google directory (Krzysztof) Changes since v2: - Fixup pinctrl@174d0000: interrupts: [..] is too long DTC warning (Tudor) - Add missing windowed watchdog code (Guenter) - Fixup UART YAML bindings error (Krzysztof) - gs101.dtsi add missing serial_0 alias (me) - samsung_tty.c: fixup gs101_serial_drv_data so fifosize is obtained from DT Changes since v1: - Remove irq/gs101.h and replace macros with irq numbers globally - exynos-pmu - keep alphabetical order - add cmu_apm to clock bindings documentation - sysreg bindings - remove superfluous `google,gs101-sysreg` - watchdog bindings - Alphanumerical order, update gs201 comment - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order - samsung,pinctrl- add google,gs101-wakeup-eint compatible - clk-pll: fixup typos - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) - clk-gs101: fix alphabetical order - clk-gs101: cmu_apm: fixup typo and missing empty entry - clk-gs101: cmu_misc: remove clocks that were being registerred twice - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter - watchdog: s3c2410_wdt: remove dev_info prints - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix - gs101-oriole.dtso: Remove overlay until board_id is documented properly - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones - gpio-keys: update linux,code to use input-event-code macros - add dedicated gs101-uart compatible Peter Griffin (19): dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: serial: samsung: Add google-gs101-uart compatible dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro watchdog: s3c2410_wdt: Add support for Google gs101 SoC tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data arm64: dts: exynos: google: Add initial Google gs101 SoC support arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support MAINTAINERS: add entry for Google Tensor SoC Tudor Ambarus (1): dt-bindings: soc: samsung: usi: add google,gs101-usi compatible .../devicetree/bindings/arm/google.yaml | 53 + .../bindings/clock/google,gs101-clock.yaml | 106 + .../samsung,pinctrl-wakeup-interrupt.yaml | 1 + .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + .../bindings/serial/samsung_uart.yaml | 11 + .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../bindings/soc/samsung/exynos-usi.yaml | 1 + .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + .../bindings/watchdog/samsung-wdt.yaml | 8 +- MAINTAINERS | 10 + arch/arm64/boot/dts/exynos/Makefile | 2 + arch/arm64/boot/dts/exynos/google/Makefile | 4 + .../boot/dts/exynos/google/gs101-oriole.dts | 105 + .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 1249 ++++++++ .../boot/dts/exynos/google/gs101-pinctrl.h | 33 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 476 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2512 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 6 + drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 + drivers/pinctrl/samsung/pinctrl-exynos.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + drivers/tty/serial/samsung_tty.c | 16 + drivers/watchdog/s3c2410_wdt.c | 87 +- include/dt-bindings/clock/google,gs101.h | 392 +++ 27 files changed, 5215 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/exynos/google/Makefile create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/google,gs101.h