| Message ID | 20230501192432.1220727-1-bhupesh.sharma@linaro.org |
|---|---|
| Headers | show |
| Series | Enable USB SS qmp phy for Qualcomm SM6115 SoC | expand |
On 01/05/2023 22:24, Bhupesh Sharma wrote: > Add support for the new qcm2290 / sm6115 binding. > > The USB QMP phy on these devices supports 2 lanes. Also note that the > binding now does not describe every register subregion and instead > the driver holds the corresponding offsets. This also includes > the PCS_MISC region. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > index a49711c5a63d..aa143c081805 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > @@ -1414,6 +1414,10 @@ struct qmp_usb_offsets { > u16 pcs_usb; > u16 tx; > u16 rx; > + /* for PHYs with >= 2 lanes */ > + u16 tx2; > + u16 rx2; > + u16 pcs_misc; > }; > > /* struct qmp_phy_cfg - per-PHY initialization config */ > @@ -1558,6 +1562,16 @@ static const char * const qmp_phy_vreg_l[] = { > "vdda-phy", "vdda-pll", > }; > > +static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { > + .serdes = 0, > + .pcs = 0xc00, > + .tx = 0x200, > + .rx = 0x400, > + .tx2 = 0x600, > + .rx2 = 0x800, > + .pcs_misc = 0xa00, > +}; > + > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { > .serdes = 0, > .pcs = 0x0200, > @@ -1922,6 +1936,8 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { > static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { > .lanes = 2, > > + .offsets = &qmp_usb_offsets_v3, > + > .serdes_tbl = qcm2290_usb3_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), > .tx_tbl = qcm2290_usb3_tx_tbl, > @@ -2497,6 +2513,12 @@ static int qmp_usb_parse_dt(struct qmp_usb *qmp) > qmp->tx = base + offs->tx; > qmp->rx = base + offs->rx; > > + if (cfg->lanes >= 2) { > + qmp->tx2 = base + offs->tx2; > + qmp->rx2 = base + offs->rx2; > + qmp->pcs_misc = base + offs->pcs_misc; pcs_misc should also be usable for a single-lane PHYs. > + } > + > qmp->pipe_clk = devm_clk_get(dev, "pipe"); > if (IS_ERR(qmp->pipe_clk)) { > return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
On 01/05/2023 22:24, Bhupesh Sharma wrote: > Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts > index dc80f0bca767..eae3024ce003 100644 > --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts > +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts > @@ -222,6 +222,30 @@ &uart4 { > status = "okay"; > }; > > +&usb { > + status = "okay"; > +}; > + > +&usb_dwc3 { > + maximum-speed = "super-speed"; > + dr_mode = "peripheral"; > +}; > + > +&usb_hsphy { > + vdd-supply = <&vreg_l4a_0p9>; > + vdda-pll-supply = <&vreg_l12a_1p8>; > + vdda-phy-dpdm-supply = <&vreg_l15a_3p128>; > + > + status = "okay"; > +}; > + > +&usb_qmpphy { > + vdda-phy-supply = <&vreg_l4a_0p9>; > + vdda-pll-supply = <&vreg_l12a_1p8>; > + > + status = "okay"; > +}; > + > &xo_board { > clock-frequency = <19200000>; > };
On 01/05/2023 22:24, Bhupesh Sharma wrote: > Add USB superspeed qmp phy node to dtsi. > > Make sure that the various board dts files (which include sm4250.dtsi file) > continue to work as intended. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++ > arch/arm64/boot/dts/qcom/sm6115.dtsi | 29 +++++++++++++++++-- > .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++ > 3 files changed, 33 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 01/05/2023 22:24, Bhupesh Sharma wrote: > Add USB superspeed qmp phy node to dtsi. > > Make sure that the various board dts files (which include sm4250.dtsi file) > continue to work as intended. > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++ > arch/arm64/boot/dts/qcom/sm6115.dtsi | 29 +++++++++++++++++-- > .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++ > 3 files changed, 33 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > index a1f0622db5a0..75951fd439df 100644 > --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > @@ -242,6 +242,9 @@ &usb { > &usb_dwc3 { > maximum-speed = "high-speed"; > dr_mode = "peripheral"; > + > + phys = <&usb_hsphy>; > + phy-names = "usb2-phy"; > }; > > &usb_hsphy { > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 631ca327e064..21d00b0295a1 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 { > status = "disabled"; > }; > > + usb_qmpphy: phy@1615000 { > + compatible = "qcom,sm6115-qmp-usb3-phy"; > + reg = <0x0 0x01615000 0x0 0x200>; I replied with R-B, but then I noticed that the length of the region is bad. What is the maximum offset that is used by the driver? I know that it is bigger than 0x200. > + > + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "cfg_ahb", > + "ref", > + "com_aux", > + "pipe"; > + > + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, > + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; > + reset-names = "phy", "phy_phy"; > + > + #clock-cells = <0>; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > qfprom@1b40000 { > compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; > reg = <0x0 0x01b40000 0x0 0x7000>; > @@ -1111,8 +1136,8 @@ usb_dwc3: usb@4e00000 { > compatible = "snps,dwc3"; > reg = <0x0 0x04e00000 0x0 0xcd00>; > interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > - phys = <&usb_hsphy>; > - phy-names = "usb2-phy"; > + phys = <&usb_hsphy>, <&usb_qmpphy>; > + phy-names = "usb2-phy", "usb3-phy"; > iommus = <&apps_smmu 0x120 0x0>; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts > index ea3340d31110..81fdcaf48926 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts > +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts > @@ -306,6 +306,9 @@ &usb { > &usb_dwc3 { > maximum-speed = "high-speed"; > dr_mode = "peripheral"; > + > + phys = <&usb_hsphy>; > + phy-names = "usb2-phy"; > }; > > &usb_hsphy {
On Tue, 2 May 2023 at 05:48, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 01/05/2023 22:24, Bhupesh Sharma wrote: > > Add USB superspeed qmp phy node to dtsi. > > > > Make sure that the various board dts files (which include sm4250.dtsi file) > > continue to work as intended. > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++ > > arch/arm64/boot/dts/qcom/sm6115.dtsi | 29 +++++++++++++++++-- > > .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++ > > 3 files changed, 33 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > > index a1f0622db5a0..75951fd439df 100644 > > --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > > +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > > @@ -242,6 +242,9 @@ &usb { > > &usb_dwc3 { > > maximum-speed = "high-speed"; > > dr_mode = "peripheral"; > > + > > + phys = <&usb_hsphy>; > > + phy-names = "usb2-phy"; > > }; > > > > &usb_hsphy { > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > index 631ca327e064..21d00b0295a1 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 { > > status = "disabled"; > > }; > > > > + usb_qmpphy: phy@1615000 { > > + compatible = "qcom,sm6115-qmp-usb3-phy"; > > + reg = <0x0 0x01615000 0x0 0x200>; > > I replied with R-B, but then I noticed that the length of the region is > bad. What is the maximum offset that is used by the driver? I know that > it is bigger than 0x200. Sure, let me recheck and fix this in the next version. Thanks, Bhupesh
On Tue, 2 May 2023 at 05:43, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 01/05/2023 22:24, Bhupesh Sharma wrote: > > Add support for the new qcm2290 / sm6115 binding. > > > > The USB QMP phy on these devices supports 2 lanes. Also note that the > > binding now does not describe every register subregion and instead > > the driver holds the corresponding offsets. This also includes > > the PCS_MISC region. > > > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > > index a49711c5a63d..aa143c081805 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c > > @@ -1414,6 +1414,10 @@ struct qmp_usb_offsets { > > u16 pcs_usb; > > u16 tx; > > u16 rx; > > + /* for PHYs with >= 2 lanes */ > > + u16 tx2; > > + u16 rx2; > > + u16 pcs_misc; > > }; > > > > /* struct qmp_phy_cfg - per-PHY initialization config */ > > @@ -1558,6 +1562,16 @@ static const char * const qmp_phy_vreg_l[] = { > > "vdda-phy", "vdda-pll", > > }; > > > > +static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { > > + .serdes = 0, > > + .pcs = 0xc00, > > + .tx = 0x200, > > + .rx = 0x400, > > + .tx2 = 0x600, > > + .rx2 = 0x800, > > + .pcs_misc = 0xa00, > > +}; > > + > > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { > > .serdes = 0, > > .pcs = 0x0200, > > @@ -1922,6 +1936,8 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { > > static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { > > .lanes = 2, > > > > + .offsets = &qmp_usb_offsets_v3, > > + > > .serdes_tbl = qcm2290_usb3_serdes_tbl, > > .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), > > .tx_tbl = qcm2290_usb3_tx_tbl, > > @@ -2497,6 +2513,12 @@ static int qmp_usb_parse_dt(struct qmp_usb *qmp) > > qmp->tx = base + offs->tx; > > qmp->rx = base + offs->rx; > > > > + if (cfg->lanes >= 2) { > > + qmp->tx2 = base + offs->tx2; > > + qmp->rx2 = base + offs->rx2; > > + qmp->pcs_misc = base + offs->pcs_misc; > > pcs_misc should also be usable for a single-lane PHYs. Ok. I will make it generic in the next version. Thanks, Bhupesh
Changes since v8: ----------------- - v8 can be seen here: https://lore.kernel.org/linux-arm-msm/20230410171010.2561393-1-bhupesh.sharma@linaro.org/ - Added driver change for new bindings used for sm6115 / qcm2290 devices. Changes since v7: ----------------- - v7 can be seen here: https://lore.kernel.org/linux-arm-msm/20230409200934.2329297-1-bhupesh.sharma@linaro.org/ - Addressed review comments from Dmitry and added "pipe clk". Changes since v6: ----------------- - v6 can be seen here: https://lore.kernel.org/linux-arm-msm/20230407061122.2036838-1-bhupesh.sharma@linaro.org/ - Addressed review comments from Bjorn and Dmitry and dropped old bindings in this version. Changes since v5: ----------------- - v5 can be seen here: https://lore.kernel.org/linux-arm-msm/20230405191633.1864671-1-bhupesh.sharma@linaro.org/ - Addressed review comments from Dmitry and made [PATCH 1/2] compatible with his 'split away legacy USB+DP code' series: <https://patchwork.kernel.org/project/linux-phy/cover/20230324215550.1966809-1-dmitry.baryshkov@linaro.org> Changes since v4: ----------------- - v4 can be seen here: https://lore.kernel.org/linux-arm-msm/20230401154725.1059563-1-bhupesh.sharma@linaro.org/ - Collected Krzysztof's Ack for [PATCH 1/2]. - Added more descriptive commit logs as per Dmitry's comments on v4. Changes since v3: ----------------- - v3 can be seen here: https://lore.kernel.org/linux-arm-msm/20221215094532.589291-4-bhupesh.sharma@linaro.org/ - Fixed v4 as per the downstream driver code: https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/bengal-usb.dtsi#296 This patchset adds the support for USB SS qmp phy for Qualcomm SM6115 SoC. For the previous versions of this patch there were conversations on irc as to whether this was a 'qcom,usb-ssphy-qmp-usb3-or-dp' or a 'qcom,usb-ssphy-qmp-dp-combo' as per downstream code and hardware documentation. But after a careful look at downstream dtsi (see [1]) it appears that this indeed is a 'qcom,usb-ssphy-qmp-usb3-or-dp' phy and not a 'dp-combo' phy. [1]. https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/bengal-usb.dtsi#296 Bhupesh Sharma (4): dt-bindings: phy: qcom,qmp-usb: Drop legacy bindings and move to newer one (SM6115 & QCM2290) phy: qcom-qmp-usb: add support for updated qcm2290 / sm6115 binding arm64: dts: qcom: sm6115: Add USB SS qmp phy node arm64: dts: qcom: qrb4210-rb2: Enable USB node .../phy/qcom,msm8996-qmp-usb3-phy.yaml | 27 ------------ .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 44 ++++++++++++++++--- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 24 ++++++++++ .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 29 +++++++++++- .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 22 ++++++++++ 7 files changed, 118 insertions(+), 34 deletions(-)