| Message ID | 20230111123711.32020-1-allen-kh.cheng@mediatek.com |
|---|---|
| Headers | show |
| Series | Add and update some driver nodes for MT8186 SoC | expand |
Hi, On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > > Add display nodes and GCE info for MT8186 SoC. Also, add GCE > (Global Command Engine) properties to the display nodes in order to > enable the usage of the CMDQ (Command Queue), which is required for > operating the display. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++++++++++++++++++++++ > 1 file changed, 128 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index eab30ab01572..8670d37970ef 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -5,6 +5,7 @@ > */ > /dts-v1/; > #include <dt-bindings/clock/mt8186-clk.h> > +#include <dt-bindings/gce/mt8186-gce.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/memory/mt8186-memory-port.h> > @@ -632,6 +633,15 @@ > clocks = <&clk13m>; > }; > > + gce: mailbox@1022c000 { > + compatible = "mediatek,mt8186-gce"; > + reg = <0 0X1022c000 0 0x4000>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <2>; > + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; > + clock-names = "gce"; > + }; > + > scp: scp@10500000 { > compatible = "mediatek,mt8186-scp"; > reg = <0 0x10500000 0 0x40000>, > @@ -1197,6 +1207,20 @@ > reg = <0 0x14000000 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, > + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > + }; > + > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8186-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; > + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > }; > > smi_common: smi@14002000 { > @@ -1230,6 +1254,49 @@ > power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > }; > > + ovl0: ovl@14005000 { If there's only one instance, you could drop the trailing zero. Same for all the other nodes. > + compatible = "mediatek,mt8186-disp-ovl", > + "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; > + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > + }; > + > + ovl0_2l: ovl@14006000 { I think this should be "ovl_2l0" or "ovl_2l" instead? > + compatible = "mediatek,mt8186-disp-ovl-2l", > + "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; > + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + }; Also, this patch is missing the aliases for ovl* and rdma*. Without them the display driver doesn't properly detect the second pipeline, and only one CRTC is generated. ChenYu
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > > Add MTU3 nodes for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > > Add DPI node for MT8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index c52f9be1e750..eab30ab01572 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -1230,6 +1230,23 @@ > power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > }; > > + dpi0: dpi@1400a000 { You could drop the trailing 0 in the label, since there is only one instance. Tested-by: Chen-Yu Tsai <wenst@chromium.org> > + compatible = "mediatek,mt8186-dpi"; > + reg = <0 0x1400a000 0 0x1000>; > + clocks = <&topckgen CLK_TOP_DPI>, > + <&mmsys CLK_MM_DISP_DPI>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + assigned-clocks = <&topckgen CLK_TOP_DPI>; > + assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; > + status = "disabled"; > + > + port { > + dpi_out: endpoint { }; > + }; > + }; > + > dsi0: dsi@14013000 { > compatible = "mediatek,mt8186-dsi"; > reg = <0 0x14013000 0 0x1000>; > -- > 2.18.0 >
This series is based on matthias github, for-next. Allen-KH Cheng (9): arm64: dts: mediatek: mt8186: Add MTU3 nodes dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi arm64: dts: mediatek: mt8186: Add SPMI node arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes arm64: dts: mediatek: mt8186: Add ADSP node arm64: dts: mediatek: mt8186: Add audio controller node arm64: dts: mediatek: mt8186: Add DPI node dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr arm64: dts: mediatek: mt8186: Add display nodes .../display/mediatek/mediatek,ccorr.yaml | 2 +- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 +- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 335 ++++++++++++++++++ 3 files changed, 344 insertions(+), 4 deletions(-)