Message ID | 20220923131148.6678-1-allen-kh.cheng@mediatek.com |
---|---|
Headers | show |
Series | Add some driver nodes for MT8186 SoC | expand |
Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > Add iommu and smi nodes for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 173 +++++++++++++++++++++++ > 1 file changed, 173 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 833e7037fe22..68f06bef88f3 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -7,6 +7,7 @@ > #include <dt-bindings/clock/mt8186-clk.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/memory/mt8186-memory-port.h> > #include <dt-bindings/pinctrl/mt8186-pinfunc.h> > #include <dt-bindings/power/mt8186-power.h> > #include <dt-bindings/phy/phy.h> > @@ -944,24 +945,113 @@ > #reset-cells = <1>; > }; > > + smi_common: smi@14002000 { > + compatible = "mediatek,mt8186-smi-common"; > + reg = <0 0x14002000 0 0x1000>; > + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; > + clock-names = "apb", "smi", "gals0", "gals1"; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > + }; > + > + larb0: smi@14003000 { > + compatible = "mediatek,mt8186-smi-larb"; > + reg = <0 0x14003000 0 0x1000>; > + mediatek,larb-id = <0>; > + mediatek,smi = <&smi_common>; Order by name after reg please... compatible reg clocks clock-names mediatek,larb-id mediatek,smi power-domains > + clocks = <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_COMMON>; > + clock-names = "apb", "smi"; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > + }; > + > + larb1: smi@14004000 { > + compatible = "mediatek,mt8186-smi-larb"; > + reg = <0 0x14004000 0 0x1000>; > + mediatek,larb-id = <1>; > + mediatek,smi = <&smi_common>; > + clocks = <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_COMMON>; > + clock-names = "apb", "smi"; > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > + }; > + > + iommu_mm: iommu@14016000 { > + compatible = "mediatek,mt8186-iommu-mm"; > + reg = <0 0x14016000 0 0x1000>; > + mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 > + &larb7 &larb8 &larb9 &larb11 > + &larb13 &larb14 &larb16 &larb17 > + &larb19 &larb20>; > + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&mmsys CLK_MM_SMI_IOMMU>; > + clock-names = "bclk"; clocks clock-names interrupts mediatek,larbs power-domains ...etc :-) P.S.: Same comment for the other commits, too! Regards, Angelo
Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > Add power domains controller for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ > 1 file changed, 188 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 64693c17af9e..833e7037fe22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -329,6 +329,194 @@ > #interrupt-cells = <2>; > }; > > + scpsys: syscon@10006000 { > + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; > + reg = <0 0x10006000 0 0x1000>; > + > + /* System Power Manager */ > + spm: power-controller { > + compatible = "mediatek,mt8186-power-controller"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + ..snip.. > + power-domain@MT8186_POWER_DOMAIN_DIS { > + reg = <MT8186_POWER_DOMAIN_DIS>; > + clocks = <&topckgen CLK_TOP_DISP>, > + <&topckgen CLK_TOP_MDP>, > + <&mmsys CLK_MM_SMI_INFRA>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_GALS>, > + <&mmsys CLK_MM_SMI_IOMMU>; > + clock-names = "dis0", "dis1", "dis-0", "dis-1", > + "dis-2", "dis-3"; What about using more descriptive names for clock-names? disp, mdp, smi_infra, smi_common, smi_gals, smi_iommu > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_VDEC { > + reg = <MT8186_POWER_DOMAIN_VDEC>; > + clocks = <&topckgen CLK_TOP_VDEC>, > + <&vdecsys CLK_VDEC_LARB1_CKEN>; > + clock-names = "vdec0", "vdec-0"; vdec0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM { > + reg = <MT8186_POWER_DOMAIN_CAM>; > + clocks = <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_SENINF>, > + <&topckgen CLK_TOP_SENINF1>, > + <&topckgen CLK_TOP_SENINF2>, > + <&topckgen CLK_TOP_SENINF3>, > + <&topckgen CLK_TOP_CAMTM>, > + <&camsys CLK_CAM2MM_GALS>; > + clock-names = "cam0", "cam1", "cam2", "cam3", > + "cam4", "cam5", "cam-0"; cam-top, cam0, cam1, cam2, cam3, cam-tm, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IMG { > + reg = <MT8186_POWER_DOMAIN_IMG>; > + clocks = <&topckgen CLK_TOP_IMG1>, > + <&imgsys1 CLK_IMG1_GALS_IMG1>; > + clock-names = "img0", "img-0"; img-top, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_IMG2 { > + reg = <MT8186_POWER_DOMAIN_IMG2>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IPE { > + reg = <MT8186_POWER_DOMAIN_IPE>; > + clocks = <&topckgen CLK_TOP_IPE>, > + <&ipesys CLK_IPE_LARB19>, > + <&ipesys CLK_IPE_LARB20>, > + <&ipesys CLK_IPE_SMI_SUBCOM>, > + <&ipesys CLK_IPE_GALS_IPE>; > + clock-names = "ipe0", "ipe-0", "ipe-1", "ipe-2", > + "ipe-3"; ipe-top, ipe-larb0, ipe-larb1, ipe-smi, ipe-gals > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_VENC { > + reg = <MT8186_POWER_DOMAIN_VENC>; > + clocks = <&topckgen CLK_TOP_VENC>, > + <&vencsys CLK_VENC_CKE1_VENC>; > + clock-names = "venc0", "venc-0"; venc0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_WPE { > + reg = <MT8186_POWER_DOMAIN_WPE>; > + clocks = <&topckgen CLK_TOP_WPE>, > + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, > + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; > + clock-names = "wpe0", "wpe-0", "wpe-1"; wpe0, larb-ck, larb-pclk Regards, Angelo
Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > Add xhci nodes for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 41 ++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index c6809fdc7d15..b08af431e525 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -845,6 +845,26 @@ > status = "disabled"; > }; > > + xhci0: usb@11200000 { Is there really no MTU3? Regards, Angelo
Hi Angelo, On Tue, 2022-09-27 at 15:40 +0200, AngeloGioacchino Del Regno wrote: > Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > > Add iommu and smi nodes for mt8186 SoC. > > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > --- > > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 173 > > +++++++++++++++++++++++ > > 1 file changed, 173 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > > index 833e7037fe22..68f06bef88f3 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > > @@ -7,6 +7,7 @@ > > #include <dt-bindings/clock/mt8186-clk.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/memory/mt8186-memory-port.h> > > #include <dt-bindings/pinctrl/mt8186-pinfunc.h> > > #include <dt-bindings/power/mt8186-power.h> > > #include <dt-bindings/phy/phy.h> > > @@ -944,24 +945,113 @@ > > #reset-cells = <1>; > > }; > > > > + smi_common: smi@14002000 { > > + compatible = "mediatek,mt8186-smi-common"; > > + reg = <0 0x14002000 0 0x1000>; > > + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys > > CLK_MM_SMI_COMMON>, > > + <&mmsys CLK_MM_SMI_GALS>, <&mmsys > > CLK_MM_SMI_GALS>; > > + clock-names = "apb", "smi", "gals0", "gals1"; > > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > > + }; > > + > > + larb0: smi@14003000 { > > + compatible = "mediatek,mt8186-smi-larb"; > > + reg = <0 0x14003000 0 0x1000>; > > + mediatek,larb-id = <0>; > > + mediatek,smi = <&smi_common>; > > Order by name after reg please... > > compatible > reg > clocks > clock-names > mediatek,larb-id > mediatek,smi > power-domains > Ok, no problem. In the next version, I will solve this. Thanks, Allen > > + clocks = <&mmsys CLK_MM_SMI_COMMON>, > > + <&mmsys CLK_MM_SMI_COMMON>; > > + clock-names = "apb", "smi"; > > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > > + }; > > + > > + larb1: smi@14004000 { > > + compatible = "mediatek,mt8186-smi-larb"; > > + reg = <0 0x14004000 0 0x1000>; > > + mediatek,larb-id = <1>; > > + mediatek,smi = <&smi_common>; > > + clocks = <&mmsys CLK_MM_SMI_COMMON>, > > + <&mmsys CLK_MM_SMI_COMMON>; > > + clock-names = "apb", "smi"; > > + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; > > + }; > > + > > + iommu_mm: iommu@14016000 { > > + compatible = "mediatek,mt8186-iommu-mm"; > > + reg = <0 0x14016000 0 0x1000>; > > + mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 > > + &larb7 &larb8 &larb9 &larb11 > > + &larb13 &larb14 &larb16 > > &larb17 > > + &larb19 &larb20>; > > + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH > > 0>; > > + clocks = <&mmsys CLK_MM_SMI_IOMMU>; > > + clock-names = "bclk"; > > clocks > clock-names > interrupts > mediatek,larbs > power-domains > > ...etc :-) > > P.S.: Same comment for the other commits, too! > > Regards, > Angelo > >