From patchwork Fri Jun 24 03:09:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 1647496 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LThv73Q7Tz9sFk for ; Fri, 24 Jun 2022 13:10:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbiFXDKJ (ORCPT ); Thu, 23 Jun 2022 23:10:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230476AbiFXDKB (ORCPT ); Thu, 23 Jun 2022 23:10:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0729035DE9; Thu, 23 Jun 2022 20:09:59 -0700 (PDT) X-UUID: 45f261b4fd574dfba6d430ae40efa86f-20220624 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:9e94d98d-4ef7-4c45-9adb-2a2c935f5650,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:c2d05638-5e4b-44d7-80b2-bb618cb09d29,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 45f261b4fd574dfba6d430ae40efa86f-20220624 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1068649577; Fri, 24 Jun 2022 11:09:50 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 24 Jun 2022 11:09:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Fri, 24 Jun 2022 11:09:48 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v14 00/15] drm/mediatek: Add MT8195 dp_intf driver Date: Fri, 24 Jun 2022 11:09:31 +0800 Message-ID: <20220624030946.14961-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work. This series is separated from [1] which is original from Guillaume. The display port driver is [2]. Changes for v14: 1. Separate a new binding patch to modify mediatek string format. 2. Use GENMASK(4, 0) for INT_MATRIX_SEL_MASK in patch "Add YUV422 output support" 3. Change kernel doc description of support_direct_pin. 4. Change to use pixels_per_iter to control quantity of transferred pixels per iterration. Changes for v13: 1. Change mediatek,mt8195-dp_intf to mediatek,mt8195-dp-intf. 2. Add kernel doc for mtk_dpi_conf. 3. Drop patch of tvd_pll enable. 4. Squash some color format transfer related patches. 5. Add new patch to support setting of direct connection to pins. 6. Change fix tag of "drm/mediatek: dpi: Only enable dpi after the bridge is enabled". Changes for v12: 1. Remove pll_gate. 2. Add more detailed commit message. 3. Separate tvd_clk patch and yuv422 output support from add dpintf support patch 4. Remove limit patch and use common driver codes to determine this. Changes for v11: 1. Rename ck_cg to pll_gate. 2. Add some commit message to clarify the modification reason. 3. Fix some driver order and modify for reviewers' comments. [1]:https://lore.kernel.org/all/20220523104758.29531-1-granquet@baylibre.com/ [2]:https://lore.kernel.org/all/20220610105522.13449-1-rex-bc.chen@mediatek.com/ Bo-Chen Chen (5): dt-bindings: mediatek,dpi: Revise mediatek strings to correct format drm/mediatek: dpi: Add kernel document for struct mtk_dpi_conf drm/mediatek: dpi: Add support for quantization range drm/mediatek: dpi: Add YUV422 output support drm/mediatek: dpi: add config to support direct connection to dpi panels Guillaume Ranquet (9): drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dp_intf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled Markus Schneider-Pargmann (1): dt-bindings: mediatek,dpi: Add DP_INTF compatible .../display/mediatek/mediatek,dpi.yaml | 11 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 268 +++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 15 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 6 files changed, 252 insertions(+), 50 deletions(-) Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno