From patchwork Mon Jun 20 12:10:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 1645479 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LRT4l0VGrz9sFw for ; Mon, 20 Jun 2022 22:10:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242145AbiFTMKo (ORCPT ); Mon, 20 Jun 2022 08:10:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242102AbiFTMKl (ORCPT ); Mon, 20 Jun 2022 08:10:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B3051834E; Mon, 20 Jun 2022 05:10:38 -0700 (PDT) X-UUID: 8e952cd87254483fbde6e43b48ba54b9-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:7b698a67-3fc3-42d1-beb3-5611c14b2536,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:b14ad71,CLOUDID:6a37333d-9948-4b2a-a784-d8a6c1086106,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 8e952cd87254483fbde6e43b48ba54b9-20220620 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 92012483; Mon, 20 Jun 2022 20:10:31 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 20 Jun 2022 20:10:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 20:10:29 +0800 From: Bo-Chen Chen To: , , , , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v12 00/14] drm/mediatek: Add MT8195 dp_intf driver Date: Mon, 20 Jun 2022 20:10:14 +0800 Message-ID: <20220620121028.29234-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work. This series is separated from [1] which is original from Guillaume. The display port driver is [2]. Changes for v12: 1. Remove pll_gate. 2. Add more detailed commit message. 3. Separate tvd_clk patch and yuv422 output support from add dpintf support patch 4. Remove limit patch and use common driver codes to determine this. Changes for v11: 1. Rename ck_cg to pll_gate. 2. Add some commit message to clarify the modification reason. 3. Fix some driver order and modify for reviewers' comments. [1]:https://lore.kernel.org/all/20220523104758.29531-1-granquet@baylibre.com/ [2]:https://lore.kernel.org/all/20220610105522.13449-1-rex-bc.chen@mediatek.com/ Bo-Chen Chen (3): drm/mediatek: dpi: Add support for quantization range drm/mediatek: dpi: Add tvd_clk enable/disable flow drm/mediatek: dpi: Add YUV422 output support Guillaume Ranquet (10): drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dpintf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled drm/mediatek: dpi: Add matrix_sel helper Markus Schneider-Pargmann (1): dt-bindings: mediatek,dpi: Add DP_INTF compatible .../display/mediatek/mediatek,dpi.yaml | 11 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 248 +++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 16 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 6 files changed, 235 insertions(+), 48 deletions(-) Reviewed-by: CK Hu Reviewed-by: CK Hu