| Message ID | 20220610092414.1816571-1-claudiu.beznea@microchip.com |
|---|---|
| Headers | show |
| Series | power: reset: at91-reset: add support for sama7g5 | expand |
Hi, On Fri, Jun 10, 2022 at 12:24:05PM +0300, Claudiu Beznea wrote: > Hi, > > The series adds reset controller support for SAMA7G5 SoCs. Compared with > previous version the reset controller embedded on SAMA7G5 is able to > reset individual on SoC devices (e.g. USB PHY controllers). > > Among with this I took the change and converted reset controller > bindings to YAML (patch 2/9) and adapt reset controller nodes in > device tree files to comply with DT specifications (patch 1/9). > > Thank you, > Claudiu Beznea Thanks, I queued patches 2-8 (i.e. skipping the DT patches). The DT patches can go through the ARM tree. In case you plan to use the dt-binding include I queued the patches via an immutable branch that can be pulled into the ARM tree: ----------------------------------------------------------------------------- The following changes since commit f2906aa863381afb0015a9eb7fefad885d4e5a56: Linux 5.19-rc1 (2022-06-05 17:18:54 -0700) are available in the Git repository at: ssh://git@gitolite.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git tags/at91-reset-sama7g5-signed for you to fetch changes up to a22c8e8834bcc55e44d0bae738f0915df7e6f573: power: reset: at91-reset: add support for SAMA7G5 (2022-06-17 17:20:00 +0200) ---------------------------------------------------------------- power: reset: at91-reset: add support for sama7g5 This adds reset controller support for SAMA7G5 SoCs. Compared with previous version the reset controller embedded on SAMA7G5 is able to reset individual on SoC devices (e.g. USB PHY controllers). Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> ---------------------------------------------------------------- Claudiu Beznea (7): dt-bindings: reset: convert Atmel/Microchip reset controller to YAML dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings dt-bindings: reset: add sama7g5 definitions power: reset: at91-reset: document structures and enums power: reset: at91-reset: add at91_reset_data power: reset: at91-reset: add reset_controller_dev support power: reset: at91-reset: add support for SAMA7G5 .../devicetree/bindings/arm/atmel-sysregs.txt | 15 -- .../bindings/reset/atmel,at91sam9260-reset.yaml | 68 ++++++++ drivers/power/reset/at91-reset.c | 184 +++++++++++++++++++-- include/dt-bindings/reset/sama7g5-reset.h | 10 ++ 4 files changed, 247 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml create mode 100644 include/dt-bindings/reset/sama7g5-reset.h ----------------------------------------------------------------------------- -- Sebastian
On 10.06.2022 12:24, Claudiu Beznea wrote: > Use generic name for reset controller of AT91 devices to comply with > DT specifications. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Applied to at91-dt, thanks! > --- > arch/arm/boot/dts/at91sam9260.dtsi | 2 +- > arch/arm/boot/dts/at91sam9261.dtsi | 2 +- > arch/arm/boot/dts/at91sam9263.dtsi | 2 +- > arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- > arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- > arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- > arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- > arch/arm/boot/dts/sam9x60.dtsi | 2 +- > arch/arm/boot/dts/sama5d2.dtsi | 2 +- > arch/arm/boot/dts/sama5d3.dtsi | 2 +- > arch/arm/boot/dts/sama5d4.dtsi | 2 +- > 11 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi > index 7368347c9357..9d9820db9482 100644 > --- a/arch/arm/boot/dts/at91sam9260.dtsi > +++ b/arch/arm/boot/dts/at91sam9260.dtsi > @@ -123,7 +123,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_xtal", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; > diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi > index 7adc36ca8a46..259aca565305 100644 > --- a/arch/arm/boot/dts/at91sam9261.dtsi > +++ b/arch/arm/boot/dts/at91sam9261.dtsi > @@ -603,7 +603,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_xtal", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&slow_xtal>; > diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi > index fe45d96239c9..c080df8c2312 100644 > --- a/arch/arm/boot/dts/at91sam9263.dtsi > +++ b/arch/arm/boot/dts/at91sam9263.dtsi > @@ -151,7 +151,7 @@ tcb0: timer@fff7c000 { > clock-names = "t0_clk", "slow_clk"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&slow_xtal>; > diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi > index 2ab730fd6472..09794561c7ce 100644 > --- a/arch/arm/boot/dts/at91sam9g45.dtsi > +++ b/arch/arm/boot/dts/at91sam9g45.dtsi > @@ -137,7 +137,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi > index 0785389f5507..556f35ce49e3 100644 > --- a/arch/arm/boot/dts/at91sam9n12.dtsi > +++ b/arch/arm/boot/dts/at91sam9n12.dtsi > @@ -126,7 +126,7 @@ pmc: pmc@fffffc00 { > interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; > }; > > - rstc@fffffe00 { > + reset-controller@fffffe00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi > index 730d1182c73e..12c634811820 100644 > --- a/arch/arm/boot/dts/at91sam9rl.dtsi > +++ b/arch/arm/boot/dts/at91sam9rl.dtsi > @@ -766,7 +766,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - rstc@fffffd00 { > + reset-controller@fffffd00 { > compatible = "atmel,at91sam9260-rstc"; > reg = <0xfffffd00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi > index 395e883644cd..ea3b11336c79 100644 > --- a/arch/arm/boot/dts/at91sam9x5.dtsi > +++ b/arch/arm/boot/dts/at91sam9x5.dtsi > @@ -134,7 +134,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi > index c328b67bea0c..6b1d4492444a 100644 > --- a/arch/arm/boot/dts/sam9x60.dtsi > +++ b/arch/arm/boot/dts/sam9x60.dtsi > @@ -667,7 +667,7 @@ pmc: pmc@fffffc00 { > clock-names = "td_slck", "md_slck", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "microchip,sam9x60-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k 0>; > diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi > index 89c71d419f82..60977bfd8563 100644 > --- a/arch/arm/boot/dts/sama5d2.dtsi > +++ b/arch/arm/boot/dts/sama5d2.dtsi > @@ -660,7 +660,7 @@ securam: sram@f8044000 { > ranges = <0 0xf8044000 0x1420>; > }; > > - reset_controller: rstc@f8048000 { > + reset_controller: reset-controller@f8048000 { > compatible = "atmel,sama5d3-rstc"; > reg = <0xf8048000 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi > index 8fa423c52592..2d0935ad2225 100644 > --- a/arch/arm/boot/dts/sama5d3.dtsi > +++ b/arch/arm/boot/dts/sama5d3.dtsi > @@ -1003,7 +1003,7 @@ pmc: pmc@fffffc00 { > clock-names = "slow_clk", "main_xtal"; > }; > > - reset_controller: rstc@fffffe00 { > + reset_controller: reset-controller@fffffe00 { > compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; > reg = <0xfffffe00 0x10>; > clocks = <&clk32k>; > diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi > index 7b9242664875..1e5c01898ccf 100644 > --- a/arch/arm/boot/dts/sama5d4.dtsi > +++ b/arch/arm/boot/dts/sama5d4.dtsi > @@ -726,7 +726,7 @@ pmecc: ecc-engine@ffffc070 { > }; > }; > > - reset_controller: rstc@fc068600 { > + reset_controller: reset-controller@fc068600 { > compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; > reg = <0xfc068600 0x10>; > clocks = <&clk32k>;
On 10.06.2022 12:24, Claudiu Beznea wrote: > Add reset controller node. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Applied to at91-dt, thanks! > --- > arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi > index a37e3a80392d..bb6d71e6dfeb 100644 > --- a/arch/arm/boot/dts/sama7g5.dtsi > +++ b/arch/arm/boot/dts/sama7g5.dtsi > @@ -198,6 +198,13 @@ pmc: pmc@e0018000 { > clock-names = "td_slck", "md_slck", "main_xtal"; > }; > > + reset_controller: reset-controller@e001d000 { > + compatible = "microchip,sama7g5-rstc"; > + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; > + #reset-cells = <1>; > + clocks = <&clk32k 0>; > + }; > + > shdwc: shdwc@e001d010 { > compatible = "microchip,sama7g5-shdwc", "syscon"; > reg = <0xe001d010 0x10>;