From patchwork Wed Jun 8 03:39:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 1640338 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LHwsZ5vPjz9sFx for ; Wed, 8 Jun 2022 15:34:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233868AbiFHFel (ORCPT ); Wed, 8 Jun 2022 01:34:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234250AbiFHFeE (ORCPT ); Wed, 8 Jun 2022 01:34:04 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A57F8224D37; Tue, 7 Jun 2022 20:40:03 -0700 (PDT) X-UUID: 342668baf1e54451af4b7c60c25dc082-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:0e3fe0de-e015-4092-8808-2840b3322881,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:0e3fe0de-e015-4092-8808-2840b3322881,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:9522927e-c8dc-403a-96e8-6237210dceee,C OID:76596dfb6dd8,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: 342668baf1e54451af4b7c60c25dc082-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1111795915; Wed, 08 Jun 2022 11:39:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 11:39:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 11:39:52 +0800 From: Bo-Chen Chen To: , , , CC: , , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v5 0/3] MediaTek MT8195 display binding Date: Wed, 8 Jun 2022 11:39:48 +0800 Message-ID: <20220608033951.25081-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add this series to present MediaTek display binding for MT8195. The reason I send this series is Jason and Nancy's binding patches are never received by devicetree mail server. Therefore, I help them to resend binding patches. Changes for v5: 1. Fix binding check error in [1/3] and [3/3]. Changes for resend v4: 1. Rebase to v5.19-rc1 which iommu series is included. 2. Add my signed-off. 3. v4 is not received by devicetree mail server, add more cc and resend. 4. This patch is from Nancy's v22 series:[2]. [2]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=645240 Changes for v3: 1. Fix rdma and ethdr binding doc. 2. Nancy's series: [1]. 3. This series is based on linux-next: next-20220511. Changes for v2: 1. This patch is based on linux next-20220506. 2. Jason's patches are accepted and I drop them. [1]: https://lore.kernel.org/all/20220512053128.31415-1-nancy.lin@mediatek.com/ Nancy.Lin (3): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit dt-bindings: mediatek: add ethdr definition for mt8195 .../display/mediatek/mediatek,ethdr.yaml | 188 ++++++++++++++++++ .../display/mediatek/mediatek,mdp-rdma.yaml | 88 ++++++++ include/dt-bindings/reset/mt8195-resets.h | 45 +++++ 3 files changed, 321 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml