From patchwork Thu Apr 28 06:17:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QWxsZW4tS0ggQ2hlbmcgKOeoi+WGoOWLsyk=?= X-Patchwork-Id: 1623422 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Kplm05g9Bz9s2R for ; Thu, 28 Apr 2022 16:17:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243632AbiD1GVC (ORCPT ); Thu, 28 Apr 2022 02:21:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243635AbiD1GVB (ORCPT ); Thu, 28 Apr 2022 02:21:01 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87217580D6; Wed, 27 Apr 2022 23:17:47 -0700 (PDT) X-UUID: ccc9919feba64604ae56febf37595536-20220428 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:dbc5d9a1-909c-4a12-a56d-e9b566c2084d,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:dbc5d9a1-909c-4a12-a56d-e9b566c2084d,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:4826002f-6199-437e-8ab4-9920b4bc5b76,C OID:4dc67446a6dc,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: ccc9919feba64604ae56febf37595536-20220428 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 635182525; Thu, 28 Apr 2022 14:17:42 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 28 Apr 2022 14:17:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Apr 2022 14:17:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Apr 2022 14:17:19 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , , Allen-KH Cheng Subject: [PATCH v8 0/2] Add basic node support for MediaTek MT8186 SoC Date: Thu, 28 Apr 2022 14:17:15 +0800 Message-ID: <20220428061717.11197-1-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT8186 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55 and 2 CA78 cores. MT8186 share many HW IP with MT65xx series. This patchset was tested on MT8186 evaluation board to shell. Based on matthias/, v5.18-next/dts64. and add the below PATCHs - clk series: 20220409132251.31725-1-chun-jie.chen@mediatek.com - mt8186 timer compatible: 20220311130732.22706-2-allen-kh.cheng@mediatek.com - mt8186 watchdog compatible from commit 888423f98c8f in linux/kernel/git/groeck/linux-staging.git, watchdog-next - reset header from commit 457ece3a0fbf in linux/kernel/git/groeck/linux-staging.git, watchdog-next changes since v7: - add scp&auxadc node changes since v6: - remove unnecessary blank line changes since v5: - replace Mediatek a to MediaTek - use GPL-2.0-only OR BSD-2-Clause changes since v4: - correct driver clock of mt8186 - add power domains controller and clock controllers - add pinctrl, usb host, spi and i2c nodes - add node status in mt8186-evb.dts - correct some dtbs_check warnings changes since v3: - remove serial, mmc and phy patch from series. (already merged) - remove mcusysoff node - move oscillator nodes at the head of dts - change name from usb-phy to t-phy changes since v2: - add soc {} in mt8186.dtsi changes since v1: - add dt-bindings: arm: Add compatible for MediaTek MT8186 Allen-KH Cheng (2): dt-bindings: arm: Add compatible for MediaTek MT8186 arm64: dts: Add MediaTek SoC MT8186 dts and evaluation board and Makefile .../devicetree/bindings/arm/mediatek.yaml | 4 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 232 +++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 949 ++++++++++++++++++ 4 files changed, 1186 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi