From patchwork Tue Apr 19 03:32:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 1618642 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Kj8X23dSrz9sGP for ; Tue, 19 Apr 2022 13:33:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348017AbiDSDfo (ORCPT ); Mon, 18 Apr 2022 23:35:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347694AbiDSDfl (ORCPT ); Mon, 18 Apr 2022 23:35:41 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D53B2BB16; Mon, 18 Apr 2022 20:32:56 -0700 (PDT) X-UUID: e05cb8460210406d839584b0824c80e9-20220419 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:996a948d-5ab5-4ccb-9784-15cf42b933e3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:246f51ef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: e05cb8460210406d839584b0824c80e9-20220419 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 216706857; Tue, 19 Apr 2022 11:32:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 19 Apr 2022 11:32:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 19 Apr 2022 11:32:39 +0800 From: Rex-BC Chen To: , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 0/5] MediaTek MT8195 display binding Date: Tue, 19 Apr 2022 11:32:32 +0800 Message-ID: <20220419033237.23405-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add this series to present MediaTek display binding for MT8195. The reason I send this series is Jason and Nancy's binding patches are never received by devicetree mail server. Therefore, I help them to resend binding patches. All of these patches are reviewed in other series: [1]: message id: 20220415083911.5186-1-jason-jh.lin@mediatek.com [2]: message id: 20220416020749.29010-1-nancy.lin@mediatek.com This series depends on Yong's MT8195 IOMMU series: [3]: message id: 20220407075726.17771-2-yong.wu@mediatek.com Without this patch, some patches of this series will build failed. Nancy.Lin (3): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit dt-bindings: mediatek: add ethdr definition for mt8195 jason-jh.lin (2): dt-bindings: arm: mediatek: mmsys: add power and gce properties dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding .../bindings/arm/mediatek/mediatek,mmsys.yaml | 32 ++++ .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ .../display/mediatek/mediatek,mdp-rdma.yaml | 86 ++++++++++ include/dt-bindings/reset/mt8195-resets.h | 12 ++ 4 files changed, 288 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml